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| 型号： | MAX15003ATM+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 24/31页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM 48TQFN-EP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| PWM 型： | 电压模式 |
| 输出数： | 3 |
| 频率 - 最大： | 2.2MHz |
| 电源电压： | 5.5 V ~ 23 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 48-WFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
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MAX15003
Triple-Output Buck Controller with
Tracking/Sequencing
f CO ≤ SW
Type III: Compensation When f CO < f ZERO, ESR
As indicated above, the position of the output capaci-
tor’s inherent ESR zero is critical in designing an appro-
priate compensation network. When low-ESR ceramic
output capacitors are used, the ESR zero frequency
(f ZERO, ESR ) is usually much higher than unity
crossover frequency (f CO ). In this case, a Type III com-
Use the following procedure to calculate the compen-
sation network components.
1) Select a crossover frequency, f CO :
f
10
2) Calculate the LC double-pole frequency, f LC :
pensation network is recommended (see Figure 7a).
V OUT
f LC =
1
2 π× L × COUT
at 0.75 x f LC where
R I
R1
C CF
R F
C F
3) Select R F ≥ 10k ? .
4) Place a zero f Z1 =
1
2 π x R F x C F
C F =
C I
R2
V REF
-
g M
+
COMP
1
2 π × RF × 0 . 75 × fLC
5) Calculate C I for a target unity-gain crossover fre-
quency, f C :
Figure 7a. Type III Compensation Network
C I =
2 π × fCO × L × COUT × VRAMP
VIN × RF
GAIN
(dB)
4TH ASYMPTOTE
R F R I-1
Note: C I is derived by setting the total loop gain at
crossover frequency to unity, e.g., G EA (f CO ) x
G MOD (f CO ) = 1V/V. The total loop gain can be
expressed logarithmically as follows:
20 × log 10 [ 2 π × f CO × R F × C I ] +
? ?
20 × log 10 ?
? = 0 dB
( ?
3RD ASYMPTOTE
ω R F C I
1ST ASYMPTOTE
( ω R I C F ) -1
5TH ASYMPTOTE
( ω R I C CF ) -1
G MOD ( DC )
?
? 2 π × f CO ) 2 × L × C OUT ?
R 1 =
7) Place a pole (f P1 =
), at or below f ZERO,ESR .
R 1 =
8) Place a second pole (f P2 =
) at or below
= P = 5 is a good number to get about
C CF =
2ND ASYMPTOTE
(R F R I ) -1
1ST POLE 1ST ZERO 2ND POLE 3RD POLE ω (rad/sec)
(AT ORIGIN) (R F C F ) -1 (R I C I ) -1 (R F C CF ) -1
2ND ZERO
(R I C I ) -1
Figure 7b. Type III Compensation Network Response
As shown in Figure 7b, a Type III compensation net-
work introduces two zeros and three poles into the con-
trol loop. The error amplifier has a low-frequency pole
at the origin, two zeros, and higher frequency poles.
The locations of the zeros and poles should be such
that the phase margin peaks at f CO .
Set the ratios of f CO -to-f Z and f P -to-f CO equal to one
another, e.g., f CO f
f Z f CO
6) Place a second zero, f Z2 , at or below f LC thereby
determining R 1 .
1
2 π × fZ 2 × CI
1
(2 π x R 1 x C I )
1
2 π × fZERO , ESR × CI
1
2 π x R F x C CF
one-half the switching frequency.
1
π × fSW × RF
9) Calculate R2 using the following equation:
FB
60° of phase margin at f CO . Whichever technique, it is
important to place the two zeros at or below the double
R 2 = R 1 ×
V
VOUT ? VFB
pole to avoid the conditional stability issue.
24
where V FB = 0.6V.
Maxim Integrated
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