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| 型号： | MAX15058EWL+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 13/21页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 3A 9WLP |
| 产品培训模块： | Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.6 V ~ 5.17 V |
| 输入电压： | 2.7 V ~ 5.5 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 1MHz |
| 电流 - 输出： | 3A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 9-WFBGA，WLBGA |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 9-WLP（1.5x1.5） |
High-Efficiency, 3A, Current-Mode
Synchronous, Step-Down Switching Regulator
FEEDBACK
ERROR AMPLIFIER
POWER MODULATOR
OUTPUT FILTER
DIVIDER
V OUT
SLOPE
COMPENSATION
RAMP
V IN
AND LOAD
FB
C
g MC
R1
*C FF
R2
V FB
g MV
R OUT
COMP
V COMP
R C
COMPARATOR
PWM
CONTROL
LOGIC
Q HS
Q LS
L
I L
DCR
I OUT
ESR
C OUT
V OUT
R LOAD
C C
V COMP
G MOD
I OUT
R OUT = 10 AVEA(dB)/20 /g MV
REF
*NOTE: C FF IS OPTIONAL AND DESIGNED TO EXTEND THE
REGULATOR’S GAIN BANDWIDTH AND INCREASED PHASE
MARGIN FOR SOME LOW-DUTY CYCLE APPLICATIONS.
Figure 1. Peak Current-Mode Regulator Transfer Model
NOTE: THE G MOD STAGE SHOWN ABOVE MODELS THE AVERAGE CURRENT OF
THE INDUCTOR, I L , INJECTED INTO THE OUTPUT LOAD, I OUT , e.g., I L = I OUT .
THIS CAN BE USED TO SIMPLIFY/MODEL THE MODULATION/CONTROL/POWER
STATE CIRCUITRY SHOWN WITHIN THE BOXED AREA.
(
)
I L_PK = I LOAD + ? I L < min I HSCL_, I L_SAT
OUT IN OUT ) ?
? V × ( V
I RIPPLE = ? I LOAD
? V IN ?
set to 0.3). In addition, the peak inductor current, I L_PK ,
must always be below the minimum high-side current-
limit value, I HSCL , and the inductor saturation current
rating, I L_SAT .
Ensure that the following relationship is satisfied:
1
2
Input Capacitor Selection
The input capacitor reduces the peak current drawn from
the input power supply and reduces switching noise in
the device. The total input capacitance must be equal to
or greater than the value given by the following equation
to keep the input ripple voltage within the specification
and minimize the high-frequency ripple current being fed
back to the input source:
f SW is the switching frequency (1MHz), and I LOAD is the
output load. The impedance of the input capacitor at
the switching frequency should be less than that of the
input source so high-frequency switching currents do not
pass through the input source, but are instead shunted
through the input capacitor.
The input capacitor must meet the ripple current require-
ment imposed by the switching currents. The RMS input
ripple current is given by:
? V ?
? ?
where I RIPPLE is the input RMS ripple current.
Output Capacitor Selection
The key selection parameters for the output capacitor
× OUT
C IN =
I LOAD V
f SW × ? V IN_RIPPLE V IN
are capacitance, ESR, ESL, and voltage rating. The
parameters affect the overall stability, output ripple volt-
age, and transient response of the DC-DC converter.
where D V IN_RIPPLE is the maximum-allowed input ripple
voltage across the input capacitors and is recommend-
ed to be less than 2% of the minimum input voltage,
The output ripple occurs due to variations in the charge
stored in the output capacitor, the voltage drop due to
the capacitor’s ESR, and the voltage drop due to the
______________________________________________________________________________________
13
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