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参数资料
| 型号： | MAX15058EWL+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 15/21页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 3A 9WLP |
| 产品培训模块： | Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.6 V ~ 5.17 V |
| 输入电压： | 2.7 V ~ 5.5 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 1MHz |
| 电流 - 输出： | 3A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 9-WFBGA，WLBGA |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 9-WLP（1.5x1.5） |
High-Efficiency, 3A, Current-Mode
Synchronous, Step-Down Switching Regulator
L × I SKIP ? LIMIT
t OFF1 =
L x ( I SKIP ? LIMIT ? I LOAD ) x ?
2 ? 1 1 ?
?
? Q OUT =
t OFF1 isthetimeneededforinductorcurrenttoreachthe
zero-current crossing limit (~0A):
V OUT
During t ON and t OFF1 , the output capacitor stores a
charge equal to (see Figure 2):
+ ?
V IN ? V OUT V OUT ?
2
During t OFF2 (= n x t CK , number of clock cycles skipped),
output capacitor loses this charge:
the inductor’s pole frequency is shifted beyond the gain
bandwidth of the regulator. System stability is provided
with the addition of a simple series capacitor-resistor from
COMP to GND. This pole-zero combination serves to tailor
the desired response of the closed-loop system. The basic
regulator loop consists of a power modulator (comprising
the regulator’s pulse-width modulator, current sense and
slope compensation ramps, control circuitry, MOSFETs,
and inductor), the capacitive output filter and load, an
output feedback divider, and a voltage-loop error amplifier
with its associated compensation circuitry. See Figure 1.
The average current through the inductor is expressed as:
I L = G MOD × V COMP
t OFF2 = ?
L x ( I SKIP ? LIMIT LOAD ) x ?
? I
+
? V V
V IN OUT OUT ?
t OFF2 =
? Q OUT
I LOAD
2 ? 1 1 ?
?
2 xI LOAD
?
where I L is the average inductor current and G MOD is the
power modulator’s transconductance.
For a buck converter:
V OUT = R LOAD × I L
f SKIP =
( I ? I ) x t
L x I SKIP ? LIMIT
? ? C OUT IN OUT )
x ( V
V OUT ? RIPPLE = ? + R ESR,COUT ?
? ?
= LOAD L = R LOAD MOD
× G
G MOD ( DC ) = g MC ×
R LOAD
? 1 + × ? ? K S × ( 1 ? D ) ? 0.5 ? ? ?
K S = 1 + = 1 + SLOPE SW MC
S SLOPE = = V SLOPE SW
V SLOPE
( V IN ? V OUT )
S N =
Finally, frequency in skip mode is:
1
t ON + t OFF1 + t OFF2
Output ripple in skip mode is:
V OUT ? RIPPLE = V COUT ? RIPPLE + V ESR ? RIPPLE
= SKIP ? LIMIT LOAD ON
C OUT
+ R ESR,COUT x ( I SKIP ? LIMIT ? I LOAD )
? ?
? V
x ( I SKIP ? LIMIT ? I LOAD )
To limit output ripple in skip mode, size C OUT based on
the above formula. All the above calculations are appli-
cable only in skip mode.
Compensation Design Guidelines
The MAX15058 uses a fixed-frequency, peak-current-mode
control scheme to provide easy compensation and fast
transient response. The inductor peak current is monitored
on a cycle-by-cycle basis and compared to the COMP
voltage (output of the voltage error amplifier). The regula-
tor’s duty cycle is modulated based on the inductor’s peak
current value. This cycle-by-cycle control of the inductor
current emulates a controlled current source. As a result,
where R LOAD is the equivalent load resistor value.
Combining the above two relationships, the power mod-
ulator’s transfer function in terms of V OUT with respect
to V COMP is:
V OUT R × I
V COMP I L
G MOD
The peak current-mode controller’s modulator gain
is attenuated by the equivalent divider ratio of the
load resistance and the current-loop gain’s impedance.
G MOD becomes:
1
? ?
? f SW × L ?
where R LOAD = V OUT/IOUT(MAX) , f SW is the switching
frequency, L is the output inductance, D is the duty cycle
(V OUT /V IN ), and K S is a slope compensation factor cal-
culated from the following equation:
S SLOPE V × f × L × g
S N ( V IN ? V OUT )
where:
× f
t SW
L × g MC
______________________________________________________________________________________
15
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