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| 型号： | MAX15058EWL+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 18/21页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 3A 9WLP |
| 产品培训模块： | Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.6 V ~ 5.17 V |
| 输入电压： | 2.7 V ~ 5.5 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 1MHz |
| 电流 - 输出： | 3A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 9-WFBGA，WLBGA |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 9-WLP（1.5x1.5） |
High-Efficiency, 3A, Current-Mode
Synchronous, Step-Down Switching Regulator
? R LOAD K S ? ( 1 ? D ) ? 0.5 ? ?
? 1 + ?
L × f SW
R1 + R2
?
? × 2 π f C
R C = × CO OUT ×
K S ? ? ( 1 ? D ) ? 0.5 ? ?
? ESR + ?
? ?
?
?
+
?
? ?
? R LOAD
?
L × f SW
f P1 < f P2 ≤ f Z1 <
<
≈
? ?
R2 g MV × g MC × R LOAD
? ?
? ?
? 1 ?
1
?
? ?
? ? ? ?
and where the ESR is much smaller than the parallel
combination of the equivalent load resistance and the
current loop impedance, e.g.,:
Using C FF the zero-pole order is adjusted as follows:
1 1
2 π C FF R1 2 π C FF (R1|| R2)
f CO < f P3 < f Z2
Confirm the desired operation of C FF empirically. The
phase lead of C FF diminishes as the output voltage
is a smaller multiple of the reference voltage, e.g.,
below about 1V. Do not use C FF when V OUT = V FB .
Setting the Soft-Start Time
The soft-start feature ramps up the output voltage slowly,
reducing input inrush current during startup. Size the
?
?
K S ? ( 1 ? D ) ? 0.5 ? ?
?
C SS = SS SS
ESR <<
1
?
? R LOAD
+
1
L × f SW ?
?
C SS capacitor to achieve the desired soft-start time, t SS,
using:
I × t
V FB
R1 + R2 2 π f CO × C OUT
R C becomes:
R C =
×
R2 g MV × g MC
I SS , the soft-start current, is 10 F A (typ) and V FB , the
output feedback voltage threshold, is 0.6V (typ). When
using large C OUT capacitance values, the high-side
current limit can trigger during the soft-start period. To
C SS >> C OUT ×
3) Determine C C by selecting the desired first sys-
tem zero, f Z1 , based on the desired phase margin.
Typically, setting f Z1 below 1/5 of f CO provides suf-
ficient phase margin.
ensure the correct soft-start time, t SS , choose C SS large
enough to satisfy:
V OUT × I SS
(I HSCL_ ? I OUT ) × V FB
≤ CO
f Z1 =
1
2 π × C C R C
f
5
I HSCL_ is the typical high-side MOSFET current-limit
value.
C C ≥
therefore:
5
2 π × f CO × R C
4) For low duty-cycle applications, the addition of a
phase-leading capacitor (C FF in Figure 1) helps
mitigate the phase lag of the damped half-frequency
double pole. Adding a second zero near to but below
the desired crossover frequency increases both the
closed-loop phase margin and the regulator’s unity-
gain bandwidth (crossover frequency). Select the
An exte rnal tracking reference with steady-state value
between 0V and V IN - 1.8V can be applied to SS/REFIN.
In this case, connect an RC network from external track-
ing reference and SS/REFIN, as shown in Figure 4. The
recomm ended value for R SS is a pproximately 1k I . R SS
is needed to ensure that, during hiccup period, SS/
REFIN can be internally pulled down.
When an external reference is connected to SS/REFIN,
the soft-start must be provided externally.
C FF =
capacitor as follows:
1
2 π × f CO × ( R1|| R2 )
V REF_EXT
R SS
C SS
SS/REFIN
MAX15058
This guarantees the additional phase-leading zero
occurs at a frequency lower than f CO from:
f PHASE_LEAD =
1
2 π × C FF × R1
Figure 4. RC Network for External Reference at SS/REFIN
18
_____________________________________________________________________________________
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