参数资料
型号: MAX1533AETJ+T
厂商: Maxim Integrated Products
文件页数: 26/38页
文件大小: 0K
描述: IC POWER SUPPLY CONTROLER 32TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
应用: 电源控制器
输入电压: 4.5 V ~ 26 V
电流 - 电源: 15µA
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 32-WFQFN 裸露焊盘
供应商设备封装: 32-TQFN-EP(5x5)
包装: 带卷 (TR)
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
high. This turns on the synchronous-rectifier MOSFETs
with 100% duty, rapidly discharging the output capaci-
tors and clamping both outputs to ground. However,
immediately latching DL_ high typically causes slightly
negative output voltages due to the energy stored in
the output LC at the instant the OVP occurs. If the load
cannot tolerate a negative voltage, place a power
Schottky diode across the output to act as a reverse-
polarity clamp. If the condition that caused the overvolt-
age persists (such as a shorted high-side MOSFET),
the battery fuse blows. Cycle V CC below 1V or toggle
either ON3, ON5, or SHDN to clear the fault latch and
restart the SMPS controllers.
Connect OVP to V CC to disable the output overvoltage
protection.
Output Undervoltage Protection (UVP)
Each SMPS controller includes an output UVP protec-
tion circuit that begins to monitor the output 6144 clock
cycles (1 / f OSC ) after that output is enabled (ON_
pulled high). If either SMPS output voltage drops below
70% of its nominal regulation voltage and the UVP pro-
tection is enabled ( UVP = GND), the UVP circuit sets
the fault latch, pulls PGOOD low, and shuts down both
controllers using discharge mode (see the Output
Discharge (Soft-Shutdown) section). When an SMPS
output voltage drops to 0.3V, its synchronous rectifier
turns on, clamping the discharged output to GND.
Cycle V CC below 1V or toggle either ON3, ON5, or
SHDN to clear the fault latch and restart the SMPS
controllers.
Connect UVP to V CC to disable the output undervoltage
protection.
Table 5. Operating Modes Truth Table
MODE
Power-Up
Run
Output Overvoltage
Protection (OVP)
Output Undervoltage
Protection (UVP)
Discharge
Standby
Shutdown
Thermal Shutdown
Switchover Fault
CONDITION
LDO5 < UVLO threshold.
SHDN = high, ON3 or ON5 enabled.
Either output > 111% of nominal level,
OVP = low.
Either output < 70% of nominal level, UVP
is enabled 6144 clock cycles (1/f OSC )
after the output is enabled and UVP = low.
OVP is low and either SMPS output is still
high in either standby mode or shutdown
mode.
ON5 and ON3 < startup threshold,
SHDN = high.
SHDN = low.
T J > +160°C.
Excessive current on LDO3 or LDO5
switchover transistors.
COMMENTS
Transitions to discharge mode after V IN POR and after REF
becomes valid. LDO5, LDO3, REF remain active. DL_ is active
if OVP is low.
Normal operation.
Exited by POR or cycling SHDN , ON3, or ON5.
Exited by POR or cycling SHDN , ON3, or ON5. If OVP is not
high, DL3 and DL5 go high after discharge.
Discharge switch (10 Ω ) connects CSL_ to PGND. This is a
temporary state entered when LDO5 is undervoltage or on the
way to output UVLO, standby, shutdown, or thermal-shutdown
states. One SMPS can be in discharge mode while the other is
in run mode. If both outputs are discharged to 0.3V (on CSL_),
discharge mode transitions to the appropriate state.
DL_ stays high if OVP is low. LDO3, LDO5 active.
All circuitry off.
Exited by POR or cycling SHDN , ON3, or ON5.
If OVP is not high, DL3 and DL5 go high before LDO5 turns off.
Exited by POR or cycling SHDN , ON3, or ON5.
If OVP is not high, DL3 and DL5 go high before LDO5 turns off.
26
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