参数资料
型号: MAX1544ETL+
厂商: Maxim Integrated Products
文件页数: 17/42页
文件大小: 0K
描述: IC QUICK-PWM DUAL-PHASE 40-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 50
系列: Quick-PWM™
应用: 控制器,AMD Hammer
输入电压: 2 V ~ 28 V
输出数: 1
输出电压: 0.68 V ~ 1.55 V
工作温度: -40°C ~ 100°C
安装类型: 表面贴装
封装/外壳: 40-WFQFN 裸露焊盘
供应商设备封装: 40-TQFN-EP(6x6)
包装: 管件
Dual-Phase, Quick-PWM Controller for
AMD Hammer CPU Core Power Supplies
Table 1. Component Selection for Standard Multiphase Applications
MAX1544
MAX1544
DESIGNATION
Input Voltage Range
VID Output Voltage
(D4 – D0)
Suspend Voltage
(SUS, S0 – S1)
Maximum Load Current
Number of Phases ( η TOTAL )
Inductor (per Phase)
Switching Frequency
High-Side MOSFET
(N H , per phase)
Low-Side MOSFET
(N L , per phase)
Total Input Capacitance (C IN )
Total Output Capacitance
(C OUT )
Current-Sense Resistor
(R SENSE , per Phase)
AMD MOBILE COMPONENTS
Circuit of Figure 1
7V to 24V
1.5V
(D4 – D0 = 00010)
Not used
(SUS = GND)
60A
Two phases
(1) MAX1544
0.6μH Panasonic ETQP1H0R6BFA
300kHz (TON = REF)
Siliconix (1) Si7886DP or
International Rectifier (2) IRF6604
Siliconix (2) Si7442DP or
International Rectifier (2) IRF6603
(8) 10μF, 25V
Taiyo Yuden TMK432BJ106KM or
TDK C4532X5R1E106M
(4) 680μF, 2.5V
Sanyo 2R5TPD680M
1m ?
Panasonic ERJM1WTJ1M0U
AMD DESKTOP COMPONENTS
Circuit of Figure 12
7V to 24V
1.5V
(D4 – D0 = 00010)
Not used
(SUS = GND)
70A
Four phases
(1) MAX1544 + (2) MAX1980
0.7μH Panasonic ETQP2H0R7BFA
or 0.8μH Sumida CDEP105L-0R8
300kHz (TON = REF)
International Rectifier (1) IRF7811W
or Fairchild (1) FDS6694
Fairchild (2) FDS6688 or Siliconix (1) Si7442DP
(8) 10μF, 25V
Taiyo Yuden TMK432BJ106KM or
TDK C4532X5R1E106M
(5) 680μF, 2.5V
Sanyo 2R5TPD680M
1m ?
Panasonic ERJM1WTJ1M0U
After the phase-overlap mode ends, the controller auto-
matically begins with the opposite phase. For example,
if the secondary phase provided the last on-time pulse
before overlap operation began, the controller starts
switching with the main phase when overlap operation
ends.
Power-Up Sequence
The MAX1544 is enabled when SHDN is driven high
(Figure 2). The reference powers up first. Once the ref-
erence exceeds its UVLO threshold, the PWM controller
evaluates the DAC target and starts switching.
For the MAX1544, the slew-rate controller ramps up the
output voltage in 25mV increments to the proper operat-
ing voltage (see Tables 3 and 4) set by either D0 – D4
(SUS = GND) or S0 – S1 (SUS = REF or high). The ramp
rate is set with the R TIME resistor (see the Output Voltage
Transition Timing section).
The ramp rate is set with the R TIME resistor (see the
Output Voltage Transition Timing section). The con-
troller pulls VROK low until at least 3ms after the
MAX1544 reaches the target DAC code.
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