参数资料
型号: MAX1544ETL+
厂商: Maxim Integrated Products
文件页数: 8/42页
文件大小: 0K
描述: IC QUICK-PWM DUAL-PHASE 40-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 50
系列: Quick-PWM™
应用: 控制器,AMD Hammer
输入电压: 2 V ~ 28 V
输出数: 1
输出电压: 0.68 V ~ 1.55 V
工作温度: -40°C ~ 100°C
安装类型: 表面贴装
封装/外壳: 40-WFQFN 裸露焊盘
供应商设备封装: 40-TQFN-EP(6x6)
包装: 管件
Dual-Phase, Quick-PWM Controller for
AMD Hammer CPU Core Power Supplies
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V+ = 15V, V CC = V DD = V SHDN = V TON = V SKIP = V S0 = V S1 = V OVP = 5V, V FB = V CMP = V CMN = V CSP = V CSN =
1.3V, OFS = SUS = GNDS = D0 – D4 = GND; T A = -40 ° C to +100 ° C , unless otherwise specified.) (Note 5)
PARAMETER
DL_ Gate-Driver On-Resistance
SYMBOL
R ON(DL)
CONDITIONS
High state (pullup)
Low start (pulldown)
MIN
MAX
4.5
2
UNITS
?
VOLTAGE-POSITIONING AMPLIFIER
Input Offset Voltage
V OS
-2.0
+2.0
mV
Common-Mode Input Voltage
Range
Output Voltage Swing
V CM
Guaranteed by CMRR test
|V OAIN+ - V OAIN- | ≥ 10mV,
R L = 1k ? to V CC /2
V CC - V FBH
V FBL
0
2.5
300
200
V
mV
LOGIC AND I/O
SHDN Input High Voltage
SHDN Input Low Voltage
V IH
V IL
High
0.8
2.7
0.4
V
V
Three-Level Input Logic Levels
SUS, SKIP
REF
1.2
2.3
V
Low
0.8
D0 – D4 Logic Input High Voltage
D0 – D4 Logic Input Low Voltage
OVP Input High Voltage
OVP Input Low Voltage
High
1.6
2.4
V CC -
0.4
0.8
0.8
V
V
V
V
Four-Level Input Logic Levels
TON, S0 – S1
Open
3.15
3.85
V
REF
Low
1.65
2.35
0.4
Note 2: DC output accuracy specifications refer to the trip level of the error amplifier. When pulse skipping, the output slightly rises
(<0.5%) when transitioning from continuous conduction to no load.
Note 3: On-time and minimum off-time specifications are measured from 50% to 50% at the DHM and DHS pins, with LX_ forced to
GND, BST_ forced to 5V, and a 500pF capacitor from DH_ to LX_ to simulate external MOSFET gate capacitance. Actual in-
circuit times may be different due to MOSFET switching speeds.
Note 4: The output fault-blanking time is measured from the time when FB reaches the regulation voltage set by the DAC code.
During normal operation (SUS = GND), the regulation voltage is set by the VID DAC inputs (D0 – D4). During suspend mode
(SUS = REF or high), the regulation voltage is set by the suspend DAC inputs (S0 – S1).
Note 5: Specifications to T A = -40 ° C and +100 ° C are guaranteed by design and are not production tested.
8
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