参数资料
型号: MAX1716EEG+
厂商: Maxim Integrated Products
文件页数: 25/33页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM CM 24-QSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 50
PWM 型: 电流模式
输出数: 1
频率 - 最大: 550kHz
占空比: 100%
电源电压: 2 V ~ 28 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 24-SSOP(0.154",3.90mm 宽)
包装: 管件
High-Speed, Adjustable, Synchronous Step-Down
Controllers with Integrated Voltage Positioning
DL
CS
N
REF
VPS
R3
C REF
0.22 μ F
MAX1716
MAX1854
R1
R SENSE
MAX1716
MAX1854
DL
Q2
R1
MAX1855
VPS
MAX1855
CS
? ?
R 2 = R 1 ?
?
R2
PGND
a) SCALED VOLTAGE POSITION SIGNAL
Figure 6. Voltage-Positioning Configurations
the complete expression for the voltage-positioned out-
put depends only upon the value of the current-sense
resistor and the load current:
V OUT ≈ V OUT(PROG) (1 - A VPS I LOAD R SENSE )
Some applications require the addition of a positive off-
set to the output voltage to ensure that it remains within
the load specifications. The positive offset may be gen-
erated by connecting a resistive divider from REF to
VPS to CS (Figure 6a). Set R1 to 1k ? , and use the fol-
lowing equation to calculate R3:
R SENSE
PGND
b) POSITIVE NO-LOAD VOLTAGE POSITIONING
to VPS to PGND (Figure 6b). Set R1 to 1k ? , and use the
following equation to calculate R2:
ESR COUT
? ? A VPS V OUT ( PROG ) R SENSE ? ESR COUT ? ?
The MAX1716/MAX1854/MAX1855 voltage-positioning
circuit has several advantages over older circuits,
which added a fixed voltage offset on the sense point
and used a low-value resistor in series with the output.
The new circuit can use the same current-sense resis-
R 3 = R 1 ?
? 1 ?
? V REF A VPS V OUT(PROG)
? V OFFSET
?
?
tor for both voltage positioning and current-limit detec-
tion. This simultaneously provides accurate current
limiting and voltage positioning. Since the new circuit
where V REF is typically 2.0V, and V OFFSET is the
required positive offset voltage. When attenuating the
voltage-positioning signal, replace R1 with the parallel
combination of R1 and R2 (R1//R2), where R2 is the
attenuation resistor (Figure 6b).
After a load transient, the output instantly changes by
ESR COUT × ? I LOAD . Setting the load-dependent volt-
age position to match this initial load step allows the
output voltage to change by ESR COUT × ? I LOAD and
stay there as long as the load remains unchanged (see
Voltage Positioning and Effective Efficiency ). To set the
voltage position equal to the initial voltage drop gener-
ated by the output capacitor ’ s ESR, select R SENSE =
ESR COUT / (V OUT(PROG) × A VPS ).
For applications using a larger current-sense resistor,
adjust V VPS by connecting a resistive divider from CS
adjusts the output voltage within the control loop, the
voltage-positioning signal may be internally amplified.
The additional gain allows the use of low-value current-
sense resistors, so the power dissipated in this sense
resistor is significantly lower than a single resistor con-
nected directly in series with the output.
Voltage-Positioning Compensation (CC)
The voltage-positioning compensation capacitor filters
the amplified VPS signal, allowing the user to adjust the
dynamics of the voltage-positioning loop. The imped-
ance at this node is approximately 200k ? , so the pole
provided by this node can be approximated by 1 / (2 ×
π × RC). The response time is set with a 47pF to
1000pF capacitor from CC to GND.
______________________________________________________________________________________
25
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