参数资料
型号: MAX1716EEG+
厂商: Maxim Integrated Products
文件页数: 29/33页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM CM 24-QSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 50
PWM 型: 电流模式
输出数: 1
频率 - 最大: 550kHz
占空比: 100%
电源电压: 2 V ~ 28 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 24-SSOP(0.154",3.90mm 宽)
包装: 管件
High-Speed, Adjustable, Synchronous Step-Down
Controllers with Integrated Voltage Positioning
ALL ANALOG GROUNDS
CONNECT TO LOCAL PLANE ONLY
VIA TO CS
AND VPS
VIA TO GND
NEAR R SENSE
VIA TO V+
BATTERY
INPUT
GND
INPUT
C IN
MAX1717
V CC
CC
REF
V DD
Q1
R SENSE
GND
OUTPUT
Q2
D1
C OUT
GND
VIA TO
SOURCE
V OUT
OF Q2
CONNECT LOCAL ANALOG GROUND PLANE DIRECTLY TO GND FROM
L1
THE SIDE OPPOSITE THE V DD CAPACITOR GND TO AVOID V DD GROUND
CURRENTS FROM FLOWING IN THE ANALOG GROUND PLANE.
VIA TO FB
NOTES: "STAR" GROUND IS USED.
D1 IS DIRECTLY ACROSS Q2.
Figure 10. Power-Stage PC Board Layout Example
VIA TO LX
INDUCTOR DISCHARGE PATH HAS LOW DC RESISTANCE.
V CC , REF, and CC capacitors, as well as the resis-
tive-dividers connected to FB and ILIM.
3) Keep the power traces and load connections short.
This is essential for high efficiency. The use of thick
copper PC boards (2oz vs. 1oz) can enhance full-
load efficiency by 1% or more. Correctly routing PC
board traces is a difficult task that must be
approached in terms of fractions of centimeters,
where a single m ? of excess trace resistance caus-
es a measurable efficiency penalty.
4) CS and PGND connections for current limiting must
be made using Kelvin sense connections to guaran-
tee the current-limit accuracy.
5) When trade-offs in trace lengths must be made, it ’ s
preferable to allow the inductor charging path to be
made longer than the discharge path. For example,
it ’ s better to allow some extra distance between the
input capacitors and the high-side MOSFET than to
allow distance between the inductor and the low-side
MOSFET or between the inductor and the output filter
capacitor.
6) Ensure the FB connection to the output is short and
direct.
7) Route high-speed switching nodes away from sensi-
tive analog areas (CC, REF, ILIM). Make all pin-strap
control input connections (SKIP, SHDN , ILIM, etc.) to
analog ground or V CC rather than PGND or V DD .
Layout Procedure
1) Place the power components first, with ground termi-
nals adjacent (low-side MOSFET source, C IN , C OUT ,
and D1 anode). If possible, make all these connec-
tions on the top layer with wide, copper-filled areas.
2) Mount the controller IC adjacent to the low-side
MOSFET. The DL gate trace must be short and wide,
measuring 10 to 20 squares (50mils to 100mils wide
if the MOSFET is 1 inch from the controller IC).
______________________________________________________________________________________
29
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