参数资料
型号: MAX1716EEG+
厂商: Maxim Integrated Products
文件页数: 6/33页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM CM 24-QSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 50
PWM 型: 电流模式
输出数: 1
频率 - 最大: 550kHz
占空比: 100%
电源电压: 2 V ~ 28 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 24-SSOP(0.154",3.90mm 宽)
包装: 管件
High-Speed, Adjustable, Synchronous Step-Down
Controllers with Integrated Voltage Positioning
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V+ = +15V, V CC = V DD = 5V, SKIP = V CC , VPS = PGND, T A = -40 ° C to +85 ° C , unless otherwise noted.) (Note 6)
PARAMETER
Current-Limit Threshold
(Positive, Default)
SYMBOL
V ITH
CONDITIONS
V PGND - V CS , ILIM = V CC
MIN
100
TYP
MAX
140
UNITS
mV
Current-Limit Threshold
(Positive, Adjustable)
V ITH
V PGND - V CS
V ILIM = 0.5V
V ILIM = 2V (REF)
35
160
65
240
mV
V CC Undervoltage Lockout
Threshold
VGATE Lower Trip Threshold
VGATE Upper Trip Threshold
VGATE Output Low Voltage
VGATE Leakage Current
Rising edge, hysteresis = 20mV, switching
disabled below this level
Measured at FB with respect to unloaded
output voltage, falling edge
Measured at FB with respect to unloaded
output voltage, rising edge
I SINK = 1mA
High state, forced to 5.5V
4.0
-12.5
7.5
4.45
-7.5
12.5
0.4
1
V
%
%
V
μ A
GATE DRIVERS
DH Gate Driver On-Resistance
DL Gate Driver On-Resistance
R ON(DH)
R ON(DL)
V BST - V LX forced to 5V
High state (pullup)
Low state (pulldown)
5
5
1.7
?
?
LOGIC AND I/O
Logic Input High Voltage
Logic Input Low Voltage
V IH
V IL
D0 ? D4, SHDN , SKIP
D0 ? D4, SHDN , SKIP
2.4
0.8
V
V
TON = V CC (200kHz operation)
V CC - 0.4
TON Input Levels
TON = open (300kHz operation)
TON = REF (400kHz operation)
3.15
1.65
3.85
2.35
V
TON = GND (550kHz operation)
0.5
Logic Input Current
D0 ? D4 Pullup Current
TON = GND or V CC
SHDN , SKIP = GND or V CC
D0 ? D4 = GND
-3
-1
3
3
1
10
μ A
μ A
Note 2: Output voltage accuracy specifications apply to DAC voltages from 0.6V to 2.0V. Includes load-regulation error.
Note 3: When the inductor is in continuous conduction, the output voltage will have a DC regulation level higher than the error-com-
parator threshold by 50% of the ripple. In discontinuous conduction ( SKIP = GND, light load), the output voltage will have a
DC regulation level higher than the trip level by approximately 1.5% due to slope compensation.
Note 4: On-time and off-time specifications are measured from 50% to 50% at the DH pin, with LX forced to 0, BST forced to 5V, and
a 500pF capacitor from DH to LX to simulate external MOSFET gate capacitance. Actual in-circuit times may be different
due to MOSFET switching speeds.
Note 5: The MAX1854 does not have overvoltage protection.
Note 6: Specifications to -40 ° C are guaranteed by design, not production tested.
6
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