参数资料
型号: MAX1717EEG+
厂商: Maxim Integrated Products
文件页数: 10/33页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM CM 24-QSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 50
PWM 型: 电流模式
输出数: 1
频率 - 最大: 1MHz
占空比: 100%
电源电压: 4.5 V ~ 5.5 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 24-SSOP(0.154",3.90mm 宽)
包装: 管件
Dynamically Adjustable, Synchronous
Step-Down Controller for Notebook CPUs
Typical Operating Characteristics (continued)
(Circuit of Figure 1, components of Table 1, V+ = +12V, V DD = V CC = SKP/ SDN = +5V, V OUT = 1.6V, T A = +25°C, unless otherwise noted.)
A
B
C
SHUTDOWN WAVEFORM
100 μ s/div
300kHz VOLTAGE POSITIONED, CIRCUIT 2,
PWM MODE, NO LOAD
A = V OUT , 1V/div
B = INDUCTOR CURRENT, 10A/div
C = SKP/SDN, 5V/div
A
B
C
SHUTDOWN WAVEFORM
100 μ s/div
300kHz VOLTAGE POSITIONED, CIRCUIT 2,
PWM MODE, I OUT = 12A
A = V OUT , 1V/div
B = INDUCTOR CURRENT, 10A/div
C = SKP/SDN, 5V/div
Pin Description
PIN
1
2
3
4
5
6
7
NAME
V+
SKP/ SDN
TIME
FB
FBS
CC
V CC
FUNCTION
Battery Voltage Sense Connection. Connect V+ to input power source. V+ is used only for PWM one-shot
timing. DH on-time is inversely proportional to input voltage over a range of 2V to 28V.
Combined Shutdown and Skip-Mode Control. Drive SKP/ SDN to GND for shutdown. Leave SKP/ SDN open for
low-noise forced-PWM mode, or drive to V CC for normal pulse-skipping operation. Low-noise forced-PWM mode
causes inductor current recirculation at light loads and suppresses pulse-skipping operation. SKP/ SDN can also
be used to disable over/undervoltage protection circuits and clear the fault latch by forcing it to 12V < SKP/ SDN
< 15V (with otherwise normal PFM/PWM operation). Do not connect SKP/ SDN to > 15V.
Slew-Rate Adjustment Pin. Connect a resistor from TIME to GND to set the internal slew-rate clock. A 470k Ω
to 47k Ω resistor sets the clock from 38kHz to 380kHz, f SLEW = 150kHz x 120k Ω / R TIME .
Fast Feedback Input. Connect FB to the junction of the external inductor and output capacitor for nonvolt-
age-positioned circuits (Figure 1). For voltage-positioned circuits, connect FB to the junction of the external
inductor and the positioning resistor (Figure 3).
Feedback Remote-Sense Input. For nonvoltage-positioned circuits, connect FBS to V OUT directly at the
load. FBS internally connects to the integrator that fine tunes the DC output voltage. For voltage-positioned
circuits, connect FBS directly to FB near the IC to disable the FBS remote-sense integrator amplifier. To dis-
able all three integrator amplifiers, connect FBS to V CC .
Integrator Capacitor Connection. Connect a 100pF to 1000pF (470pF typ) capacitor from CC to GND to set
the integration time constant. CC can be left open if FBS is tied to V CC .
Analog Supply Voltage Input for PWM Core. Connect V CC to the system supply voltage (4.5V to 5.5V) with a
series 20 Ω resistor. Bypass to GND with a 0.22μF (min) capacitor.
10
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