参数资料
型号: MAX1717EEG+
厂商: Maxim Integrated Products
文件页数: 5/33页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM CM 24-QSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 50
PWM 型: 电流模式
输出数: 1
频率 - 最大: 1MHz
占空比: 100%
电源电压: 4.5 V ~ 5.5 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 24-SSOP(0.154",3.90mm 宽)
包装: 管件
Dynamically Adjustable, Synchronous
Step-Down Controller for Notebook CPUs
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V+ = +15V, V CC = V DD = SKP/ SDN = +5V, V OUT =1.6V, T A = -40°C to +85°C , unless otherwise noted.) (Note 3)
PARAMETER
Quiescent Supply Current (V CC )
Quiescent Supply Current (V DD )
CONDITIONS
Measured at V CC , FB forced above the regulation point
Measured at V DD , FB forced above the regulation point
MIN
TYP
MAX
1200
5
UNITS
μA
μA
Quiescent Battery Supply
Current (V+)
40
μA
Shutdown Supply Current (V CC )
Shutdown Supply Current (V DD )
Shutdown Battery Supply
Current (V+)
SKP/ SDN = 0
SKP/ SDN = 0
SKP/ SDN = 0, V CC = V DD = 0 or 5V
5
5
5
μA
μA
μA
Reference Voltage
Overvoltage Trip Threshold
Output Undervoltage Protection
Threshold
Current-Limit Threshold
(Positive, Default)
V CC = 4.5V to 5.5V, no REF load
Measured at FB
With respect to unloaded output voltage
GND - LX, ILIM = V CC
1.98
2.20
65
80
2.02
2.30
75
115
V
V
%
mV
Current-Limit Threshold
(Positive, Adjustable)
GND - LX
ILIM = 0.5V
ILIM = REF (2V)
33
160
65
240
mV
Current-Limit Threshold
(Negative)
V CC Undervoltage Lockout
Threshold
LX - GND, ILIM = V CC
Rising edge, hysteresis = 20mV, PWM disabled below this
level
-140
4.1
-80
4.4
mV
V
DH Gate Driver On-Resistance
DL Gate Driver On-Resistance
Logic Input High Voltage
Logic Input Low Voltage
DAC B-Mode Programming
Resistor, Low
DAC B-Mode Programming
Resistor, High
BST - LX forced to 5V
DL, high state (pullup)
DL, low state (pulldown)
D0–D4, A/ B
D0–D4, A/ B
D0–D4, 0 to 0.4V or 2.6V to 5.5V applied through resistor,
A/ B = GND
D0–D4, 0 to 0.4V or 2.6V to 5.5V applied through resistor,
A/ B = GND
2.4
100
3.5
3.5
1.0
0.8
1
Ω
Ω
Ω
V
V
k Ω
k Ω
VGATE Lower Trip Threshold
VGATE Upper Trip Threshold
Measured at FB with respect to unloaded output voltage,
falling edge, hysteresis = 1%
Measured at FB with respect to unloaded output voltage,
rising edge, hysteresis = 1%
-8.4
+10
-4.6
+15
%
%
Note 1: Output voltage accuracy specifications apply to DAC voltages from 0.925V to 2V. Includes load-regulation error.
Note 2: On-Time specifications are measured from 50% to 50% at the DH pin, with LX forced to 0, BST forced to 5V, and a 500pF
capacitor from DH to LX to simulate external MOSFET gate capacitance. Actual in-circuit times may be different due to
MOSFET switching speeds.
Note 3: Specifications to -40°C are guaranteed by design and not production tested.
_______________________________________________________________________________________
5
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