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参数资料
| 型号： | MAX1717EEG+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 19/33页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM CM 24-QSOP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 50 |
| PWM 型： | 电流模式 |
| 输出数： | 1 |
| 频率 - 最大： | 1MHz |
| 占空比： | 100% |
| 电源电压： | 4.5 V ~ 5.5 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 24-SSOP（0.154"，3.90mm 宽） |
| 包装： | 管件 |
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Dynamically Adjustable, Synchronous
Step-Down Controller for Notebook CPUs
short, wide traces measuring 10 to 20 squares (50 to 100
mils wide if the MOSFET is 1 inch from the MAX1717).
The dead time at the other edge (DH turning off) is
determined by a fixed 35ns (typ) internal delay.
The internal pull-down transistor that drives DL low is
robust, with a 0.5 Ω typical on-resistance. This helps
prevent DL from being pulled up during the fast rise-
time of the inductor node, due to capacitive coupling
from the drain to the gate of the low-side synchronous-
rectifier MOSFET. However, for high-current applications,
you might still encounter some combinations of high-
and low-side FETs that will cause excessive gate-drain
coupling, which can lead to efficiency-killing, EMI-
producing shoot-through currents. This is often remedied
by adding a resistor in series with BST, which increases
the turn-on time of the high-side FET without degrading
the turn-off time (Figure 6).
POR
Power-on reset (POR) occurs when V CC rises above
approximately 2V, resetting the fault latch and preparing
the PWM for operation. V CC undervoltage lockout
(UVLO) circuitry inhibits switching, forces VGATE low,
and forces the DL gate driver high (to enforce output
overvoltage protection). When V CC rises above 4.2V, the
DAC inputs are sampled and the output voltage begins
to slew to the DAC setting.
For automatic startup, the battery voltage should be
present before V CC . If the MAX1717 attempts to bring
the output into regulation without the battery voltage
present, the fault latch will trip. The SKP/ SDN pin can
be toggled to reset the fault latch.
Shutdown
When SKP/ SDN goes low, the MAX1717 goes into low-
power shutdown mode. VGATE goes low immediately.
The output voltage ramps down to 0 in 25mV steps at
the clock rate set by R TIME . When the DAC reaches the
0V setting, DL goes high, DH goes low, the reference is
turned off, and the supply current drops to about 2μA.
When SKP/ SDN goes high or floats, the reference pow-
ers up, and after the reference UVLO is passed, the
DAC target is evaluated and switching begins. The
slew-rate controller ramps up from zero in 25mV steps
to the currently selected code value (based on A/ B ).
There is no traditional soft-start (variable current limit)
circuitry, so full output current is available immediately.
VGATE goes high after the slew-rate controller has ter-
minated and the output voltage is in regulation. As soon
as VGATE goes high, full power is available.
UVLO
If the V CC voltage drops low enough to trip the UVLO
comparator, it is assumed that there is not enough supply
voltage to make valid decisions. To protect the output
from overvoltage faults, DL is forced high in this mode.
This will force the output to GND, but it will not use the
slew-rate controller. This results in large negative
inductor current and possibly small negative output
voltages. If V CC is likely to drop in this fashion, the output
can be clamped with a Schottky diode to GND to
reduce the negative excursion.
DAC Inputs D0–D4
The digital-to-analog converter (DAC) programs the
output voltage. It typically receives a preset digital
code from the CPU pins, which are either hard-wired to
GND or left open-circuit. They can also be driven by
digital logic, general-purpose I/O, or an external mux.
Do not leave D0–D4 floating—use 1M Ω or less pull-ups
if the inputs may float. D0–D4 can be changed while
the SMPS is active, initiating a transition to a new output
+5V
V BATT
voltage level. If this mode of DAC control is used, connect
A/ B high. Change D0–D4 together, avoiding greater
MAX1717
BST
DH
LX
5 Ω TYP
than 1μs skew between bits. Otherwise, incorrect DAC
readings may cause a partial transition to the wrong
voltage level, followed by the intended transition to the
correct voltage level, lengthening the overall transition
time. The available DAC codes and resulting output
voltages (Table 4) are compatible with Intel’s mobile
Pentium ? III specification.
Figure 6. Reducing the Switching-Node Rise Time
Pentium is a registered trademark of Intel Corp.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MAX1717EEG+ | 功能描述:DC/DC 开关控制器 Adj Synchronous Step-Down RoHS:否 制造商:Texas Instruments 输入电压:6 V to 100 V 开关频率: 输出电压:1.215 V to 80 V 输出电流:3.5 A 输出端数量:1 最大工作温度:+ 125 C 安装风格: 封装 / 箱体:CPAK |
| MAX1717EEG+C71058 | 功能描述:DC/DC 开关控制器 Step-Down Controller for Notebook CPU RoHS:否 制造商:Texas Instruments 输入电压:6 V to 100 V 开关频率: 输出电压:1.215 V to 80 V 输出电流:3.5 A 输出端数量:1 最大工作温度:+ 125 C 安装风格: 封装 / 箱体:CPAK |
| MAX1717EEG+T | 功能描述:DC/DC 开关控制器 Adj Synchronous Step-Down RoHS:否 制造商:Texas Instruments 输入电压:6 V to 100 V 开关频率: 输出电压:1.215 V to 80 V 输出电流:3.5 A 输出端数量:1 最大工作温度:+ 125 C 安装风格: 封装 / 箱体:CPAK |
| MAX1717EEG-C71058 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述: |
| MAX1717EEG-T | 功能描述:DC/DC 开关控制器 RoHS:否 制造商:Texas Instruments 输入电压:6 V to 100 V 开关频率: 输出电压:1.215 V to 80 V 输出电流:3.5 A 输出端数量:1 最大工作温度:+ 125 C 安装风格: 封装 / 箱体:CPAK |
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