参数资料
型号: MAX17410GTM+T
厂商: Maxim Integrated
文件页数: 18/45页
文件大小: 0K
描述: IC CTLR QPWM 2PH FOR IMV 48TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
系列: *
Dual-Phase, Quick-PWM Controller
for IMVP6+ CPU Core Power Supplies
Pin Description (continued)
PIN
32
33
34
35
36
37 –43
44
NAME
DL1
PGND1
LX1
DH1
BST1
D0 –D6
SHDN
FUNCTION
Phase 1 Low-Side Gate-Driver Output. DL1 swings from PGND1 to V DD . DL1 is forced low in
shutdown. DL1 is forced high when an output overvoltage fault is detected, overriding any
negative current-limit condition that might be present. DL1 is forced low in skip mode after
detecting an inductor current zero crossing.
Power Ground. PGND1 is the internal lower supply rail for the DL1 low-side gate driver.
Phase 1 Inductor Connection. LX1 is the internal lower supply rail for the DH1 high-side gate driver.
Also used as an input to phase 1 ’s zero-crossing comparator.
Phase 1 High-Side Gate-Driver Output. DH1 swings from LX1 to BST1. Low in shutdown.
Phase 1 Boost Flying Capacitor Connection. BST1 is the internal upper supply rail for the DH1
high-side gate driver. An internal switch between V DD and BST1 charges the BST1 - LX1 flying
capacitor, while the low-side MOSFET is on (DL1 pulled high).
Low-Voltage (1.0V Logic) VID DAC Code Inputs. The D0 –D6 inputs do not have internal pullups.
These 1.0V logic inputs are designed to interface directly with the CPU. The output voltage is set
by the VID code indicated by the logic-level voltages on D0 –D6 (see Table 4).
Shutdown Control Input. Connect to V CC for normal operation. Connect to ground to put the IC into
the 1μA (max at T A = +25 ° C) shutdown state. During startup, the output voltage is ramped up at
1/8 the slew rate set by the TIME resistor to the boot voltage. During the transition from normal
operation to shutdown, the output voltage is ramped down at 1/8 the slew rate set by the TIME
resistor. Forcing SHDN to 11V ~ 13V disables overvoltage protection, undervoltage protection, and
thermal shutdown, clears the fault latches, disables transient phase overlap, disables soar
suppression, and turns off the internal BST_-to-V DD switches. However, internal diodes still exist
between BST_ and V DD in this state.
3.3V Logic Input. Indicates power usage and sets the operating mode together with PSI as shown
in the truth table below. When DPRSLPVR is forced high, the controller is immediately set to 1-
phase automatic pulse-skipping mode. The controller returns to forced-PWM mode when
DPRSLPVR is forced low and the output is in regulation. The PWRGD upper threshold is blanked
during any downward output voltage transition that happens when the controller is in skip mode,
and stays blanked until the slew-rate-controlled internal-transition-related PWRGD blanking period
is complete and the output reaches regulation. During this blanking period, the overvoltage fault
threshold is changed from a tracking [VID + 300mV] threshold to a fixed 1.8V threshold.
DPRSLPVR
PSI
Mode
45
DPRSLPVR
1
1
0
0
0
1
0
1
Very low current (1-phase skip)
Low current (approx 3A) (1-phase skip)
Intermediate power potential (1-phase PWM)
Max power potential (full-phase PWM: 2-phase or 1-phase as set by user at
CSP2)
The controller is in 2-phase skip mode during startup, but is in 2-phase forced-PWM mode during
soft-shutdown, irrespective of the DPRSLPVR and PSI logic levels. The controller is in 2-phase skip
mode while in boot mode, but is in 2-phase forced-PWM mode during the transition from boot mode
to VID mode, irrespective of the DPRSLPVR and PSI logic levels. However, if phase 2 is disabled
by connecting CSP2 to V CC , then only phase 1 is active in the above modes.
18
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