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| 型号： | MAX17480GTL+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 18/48页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR SERIAL VID 40-TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 应用： | 处理器 |
| 电流 - 电源： | 5mA |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-WFQFN 裸露焊盘 |
| 供应商设备封装： | 40-TQFN-EP（5x5） |
| 包装： | 带卷 (TR) |
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AMD 2-/3-Output Mobile Serial
VID Controller
Pin Description (continued)
PIN
20
21
22
23
24
25
26
27
28
29
30
31
32
NAME
PWRGD
DH2
LX2
BST2
DL2
V DD
DL1
BST1
LX1
DH1
VRHOT
THRM
V CC
FUNCTION
Open-Drain Power-Good Output. PWRGD is the wired-OR open-drain output of all three SMPS
outputs.
PWRGD is forced high impedance whenever the slew-rate controller is active (output voltage
transitions).
During startup, PWRGD is held low for an additional 20μs after the MAX17480 reaches the startup
boot voltage set by the SVC and SVD pins. The MAX17480 stores the boot VID when PWRGD first
goes high. The stored boot VID is cleared by rising SHDN .
PWRGD is forced low in shutdown.
When SMPS is in pulse-skipping mode, the upper PWRGD threshold comparator for the respective
SMPS is blanked during a downward VID transition. The upper PWRGD threshold comparator is re-
enabled once the output is in regulation (Figure 6).
SMPS2 High-Side Gate-Driver Output. DH2 swings from LX2 to BST2. Low in shutdown.
SMPS2 Inductor Connection. LX2 is the internal lower supply rail for the DH2 high-side gate driver.
Also used as an input to SMPS2 ’s zero-crossing comparator.
Boost Flying Capacitor Connection for the DH2 High-Side Gate Driver. An internal switch between
V DD and BST2 charges the flying capacitor during the time the low-side FET is on.
SMPS2 Low-Side Gate-Driver Output. DL2 swings from GND2 to V DD . DL2 is forced low in shutdown.
DL2 is also forced high when an output overvoltage fault is detected. DL2 is forced low in skip
mode after an inductor current zero crossing (GND2 - LX2) is detected.
Supply Voltage Input for the DL_ Drivers. V DD is also the supply voltage used to internally recharge
the BST_ flying capacitors during the off-time. Connect V DD to the 4.5V to 5.5V system supply
voltage. Bypass V DD to GND with a 2.2μF or greater ceramic capacitor.
SMPS1 Low-Side Gate-Driver Output. DL1 swings from GND1 to V DD . DL1 is forced low in shutdown.
DL1 is also forced high when an output overvoltage fault is detected. DL1 is forced low in skip
mode after an inductor current zero crossing (GND1 - LX1) is detected.
Boost Flying Capacitor Connection for the DH1 High-Side Gate Driver. An internal switch between
V DD and BST1 charges the flying capacitor during the time the low-side FET is on.
SMPS1 Inductor Connection. LX1 is the internal lower supply rail for the DH1 high-side gate driver.
Also used as an input to SMPS1 ’s zero-crossing comparator.
SMPS1 High-Side Gate-Driver Output. DH1 swings from LX1 to BST1. Low in shutdown.
Active-Low Open-Drain Output of Internal Comparator. VRHOT is pulled low when the voltage at
THRM goes below 1.5V (30% of V CC ). VRHOT is high impedance in shutdown.
Input of Internal Comparator. Connect the output of a resistor- and thermistor-divider (between V CC
and GND) to THRM. Select the components so the voltage at THRM falls below 1.5V (30% of V CC )
at the desired high temperature.
Controller Supply Voltage. Connect to a 4.5V to 5.5V source. Bypass to GND with a 1μF minimum
capacitor. A V CC UVLO event that occurs while the IC is functioning is latched, and can only be
cleared by cycling V CC power or by toggling SHDN .
18
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