参数资料
型号: MAX17480GTL+T
厂商: Maxim Integrated Products
文件页数: 47/48页
文件大小: 0K
描述: IC CTRLR SERIAL VID 40-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
应用: 处理器
电流 - 电源: 5mA
电源电压: 4.5 V ~ 5.5 V
工作温度: -40°C ~ 105°C
安装类型: 表面贴装
封装/外壳: 40-WFQFN 裸露焊盘
供应商设备封装: 40-TQFN-EP(5x5)
包装: 带卷 (TR)
AMD 2-/3-Output Mobile Serial
VID Controller
5) Make the DC-DC controller ground connections as
shown in the standard application circuit (Figure 2).
This diagram can be viewed as having three sepa-
rate ground planes: input/output ground, where all
the high-power components go; the power ground
plane, where the PGND, V DD bypass capacitor,
and driver IC ground connection go; and the con-
troller’s analog ground plane, where sensitive ana-
log components, the MAX17480’s AGND pin, and
V CC bypass capacitor go. The controller’s analog
ground plane (AGND) must meet the power ground
plane (PGND) only at a single point directly beneath
the IC. The power ground plane should connect to
the high-power output ground with a short, thick
metal trace from PGND to the source of the low-side
MOSFETs (the middle of the star ground).
6) Connect the output power planes (V CORE , V OUT3 ,
and system ground planes) directly to the output
filter capacitor positive and negative terminals with
multiple vias. Place the entire DC-DC converter
circuit as close to the CPU as is practical.
SPLIT CORE
CPU SOCKET
V DDNB
C OUT
V CORE0
V CORE1
C OUT
KELVIN-SENSE VIAS UNDER THE INDUCTOR
C OUT
C OUT
(REFER TO EVALUATION KIT)
C VCC
C EQ
CSP
CSN
INDUCTOR
INDUCTOR
R NTC
R2
R1
CSP
CSN
+
L3
KELVIN-SENSE VIAS TO
INDUCTOR PAD
C IN
C IN
C OUT3
AGND PIN
C IN
POWER
GROUND
C IN
INDUCTOR DCR SENSING
CONNECT THE EXPOSED
PAD TO POWER GND
USING MULTIPLE VIAS
Figure 15. PCB Layout Example
______________________________________________________________________________________
47
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