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参数资料
| 型号： | MAX17480GTL+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 45/48页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR SERIAL VID 40-TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 应用： | 处理器 |
| 电流 - 电源： | 5mA |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-WFQFN 裸露焊盘 |
| 供应商设备封装： | 40-TQFN-EP（5x5） |
| 包装： | 带卷 (TR) |
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AMD 2-/3-Output Mobile Serial
VID Controller
Command Byte
A complete command consists of a START condition
(S) followed by the MAX17480’s slave address and a
data phase, followed by a STOP condition (P). For the
slave address, bits 6:4 are always 110 and bit 3 is X
(don’t care). The WR bit should always be 1 since read
functions are not supported. Figure 14 is the SVI bus
data-transfer summary. Table 7 is a description of the
SVI send byte address and Table 8 describes serial
VID 8-bit field encoding.
START
SMPS Applications Information
Duty-Cycle Limits
Minimum Input Voltage
The minimum input operating voltage (dropout voltage)
is restricted by stability requirements, not the minimum
off-time (t OFF(MIN) ). The MAX17480 does not include
slope compensation, so the controller becomes unsta-
ble with duty cycles greater than 50% per phase:
V IN(MIN) ≥ 2V OUT(MAX)
However, the controller can briefly operate with duty
cycles over 50% during heavy load transients.
STOP
S
SLAVE ADDRESS
SET DAC AND PSI_L
P
FIXED VALUES
Figure 14. SVI Bus Data Transfer Summary
Table 7. SVI Send Byte Address Description
Table 8. Serial VID 8-Bit Field Encoding
BIT
6:4
3
2
1
0
DESCRIPTION
Always 110b.
X—don ’t care.
VDD1, if set then the following data byte
contains the VID for VDD1. Bit 2 is ignored in
combined mode (GNDS1 or GNDS2 = V DDIO ).
VDD1 refers to CORE1 of the AMD CPU.
VDD0, if set then the following data byte
contains the VID for VDD0 in separate mode, and
the unified VDD in combined mode. VDD0 refers
to CORE0 of the AMD CPU.
VDDNB, if set then the following data byte
contains the VID for VDDNB.
BIT
7
6:0
DESCRIPTION
PSI_L: Power-Save Indicator
0 means the processor is at an optimal load and
the SMPS(s) can enter power-saving mode. The
SMPS operates in pulse-skipping mode after
exiting the boot mode. Offset is disabled if
previously enabled by the OPTION pin. The
MAX17480 enters 1-phase operation if in
combined mode (GNDS1 or GNDS2 = H).
1 means the processor is in a high current-
consumption state. The SMPS operates in forced-
PWM mode after exiting the boot mode. Offset is
enabled if previously enabled by the OPTION
pin. The MAX17480 returns to 2-phase operation
if in combined mode (GNDS1 or GNDS2 = H).
SVID[6:0] as defined in Table 7.
______________________________________________________________________________________
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