参数资料
型号: MAX3799ETJ+T
厂商: Maxim Integrated
文件页数: 13/36页
文件大小: 0K
描述: IC AMP LIMITING VCSEL DVR 32TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: 激光二极管驱动器
数据速率: 14Gbps
通道数: 1
电源电压: 2.85 V ~ 3.63 V
电流 - 电源: 97mA
电流 - 调制: 12mA
电流 - 偏置: 15mA
工作温度: -40°C ~ 85°C
封装/外壳: 32-WFQFN 裸露焊盘
供应商设备封装: 32-TQFN-EP(5x5)
包装: 带卷 (TR)
安装类型: 表面贴装
MAX3799
1Gbps to 14Gbps, SFP+ Multirate Limiting
Amplifier and VCSEL Driver
Typical Operating Characteristics—VCSEL Driver (continued)
(V CC = 3.3V, T A = +25°C, unless otherwise specified. Figure 1 shows the typical setup used for measurements. Registers are set to
default values unless otherwise noted, and the 3-wire interface is static during measurements. For testing, the RATE_SEL bit was
used and the RSEL pin was left open.)
DETERMINISTIC JITTER
vs. PULSE-WIDTH SETTING
BIAS MONITOR CURRENT
vs. TEMPERATURE
10
9
8
7
PATTERN = PRBS, DATA RATE = 10.32Gbps
800
700
600
500
I BIAS = 12mA
6
5
400
300
I BIAS = 8mA
4
UP
DOWN
200
I BIAS = 2mA
3
2
EYE CROSSING
100
0
-7
-5
-3
-1
1
3
5
7
-40 -25 -10
5
20
35
50
65
80
95
SET_PWCTRL[3:0]
TEMPERATURE ( ° C)
Pin Description
PIN
1
2
3, 6, 27, 30
NAME
LOS
RSEL
V CCR
FUNCTION
Loss-of-Signal Output, Open Drain. The default polarity of LOS is high when the level of the input
signal is below the preset threshold set by the SET_LOS DAC. Polarity of the LOS function can be
inverted by setting LOS_POL = 0. The LOS circuitry can be disabled by setting the bit LOS_EN = 0.
Mode-Select Input, TTL/CMOS. Set the RSEL pin or RATE_SEL bit (set by the 3-wire digital interface)
to logic-high for high-bandwidth mode. Setting RSEL and RATE_SEL logic-low for high-gain mode.
The RSEL pin is internally pulled down by a 75k
resistor to ground.
Power Supply. Provides supply voltage to the receiver block.
4
ROUT+
Noninverted Receive Data Output, CML. Back-terminated for 50
load.
5
ROUT-
Inverted Receive Data Output, CML. Back-terminated for 50
load.
7
8
V CCD
DISABLE
Power Supply. Provides supply voltage for the digital block.
Transmitter Disable Input, TTL/CMOS. Set to logic-low for normal operation. Logic-high or open
disables both the modulation and bias current. Internally pulled up by an 8k resistor to V CCT .
9
SCL
Serial-Clock Input, TTL/CMOS. This pin has a 75k
internal pulldown.
Serial-Data Bidirectional Input, TTL/CMOS. Open-drain output. This pin has a 75k
internal pullup,
10
SDA
but it requires an external 4.7k
pullup resistor to meet the 3-wire digital timing specification. (Data
line collision protection is implemented.)
Chip-Select Input, TTL/CMOS. Setting CSEL to logic-high starts a cycle. Setting CSEL to logic-low
11
CSEL
ends the cycle and resets the control state machine. Internally pulled down by a 75k
resistor to
ground.
12, 15, 18,
21, 24, 25
13
Maxim Integrated
V CCT
TIN+
Power Supply. Provides supply voltage to the transmitter block.
Noninverted Transmit Data Input, CML
13
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