参数资料
型号: MAX3799ETJ+T
厂商: Maxim Integrated
文件页数: 16/36页
文件大小: 0K
描述: IC AMP LIMITING VCSEL DVR 32TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: 激光二极管驱动器
数据速率: 14Gbps
通道数: 1
电源电压: 2.85 V ~ 3.63 V
电流 - 电源: 97mA
电流 - 调制: 12mA
电流 - 偏置: 15mA
工作温度: -40°C ~ 85°C
封装/外壳: 32-WFQFN 裸露焊盘
供应商设备封装: 32-TQFN-EP(5x5)
包装: 带卷 (TR)
安装类型: 表面贴装
MAX3799
1Gbps to 14Gbps, SFP+ Multirate Limiting
Amplifier and VCSEL Driver
Dual Path Limiter
The limiting amplifier features a low data-rate mode
(1.25Gbps) and a high data-rate mode (up to
10.32Gbps), allowing for overall system optimization.
Either the RSEL pin or the RATE_SEL bit can perform
the rate selection. For operating up to 1.25Gbps, the
low data-rate mode (RATE_SEL = 0) is recommended.
For operation up to 14.025Gbps, the high data-rate
mode (RATE_SEL = 1) is recommended. The polarity of
the ROUT+/ROUT- relative to RIN+/RIN- is pro-
grammed by the RX_POL bit.
Offset Correction Circuitry
The offset correction circuit is enabled to remove pulse-
width distortion caused by intrinsic offset voltages with-
in the differential amplifier stages. An external capacitor
(C AZ ) connected between the CAZ1 and CAZ2 pins is
used to set the offset correction loop cutoff frequency.
The offset loop can be disabled using the AZ_EN bit.
CML Output Stage with Deemphasis
and Slew-Rate Control
The CML output stage is optimized for differential 100 ?
loads. The RXDE_EN bit adds analog deemphasis
compensation to the limited differential output signal for
SFP connector losses. The output stage is controlled by
a combination of the RX_EN and SQ_EN bits and the
LOS pin. See Table 1.
Amplitude of the CML output stage is controlled by an
8-bit DAC register (SET_CML). The differential output
amplitude range is from 40mV P-P up to 1200mV P-P with
4.6mV P-P resolution (assuming an ideal 100 ? differen-
tial load).
Table 1. CML Output Stage Operation Mode
Loss-of-Signal (LOS) Circuitry
The input data amplitude is compared to a preset
threshold controlled by the 6-bit DAC register
SET_LOS. The LOS assert level can be programmed
from 14mV P-P up to 77mV P-P with 1.5mV P-P resolution
(assuming an ideal 100 ? differential source). LOS is
enabled through the LOS_EN bit and the polarity of the
LOS is controlled with the LOS_POL bit.
VCSEL Driver
The VCSEL driver inside the MAX3799 is designed to
operate from 1.0625Gbps to 10.32Gbps. The transmit-
ter contains a differential data path with pulse-width
adjustment, bias current and modulation current DACs,
output driver with programmable deemphasis, power-
on reset circuitry, BIAS monitor, VCSEL current limiter,
and eye safety circuitry. A 3-wire digital interface is
used to control the transmitter functions. The registers
that control the transmitter functionality are TXCTRL,
TXSTAT1, TXSTAT2, SET_IBIAS, SET_IMOD, IMOD-
MAX, IBIASMAX, MODINC, BIASINC, MODECTRL,
SET_PWCTRL, and SET_TXDE.
Differential Data Path
The CML input buffer is optimized for AC-coupled sig-
nals and is internally terminated with a differential
100 ? . Differential input data is equalized for high-fre-
quency losses due to SFP connectors. The TX_POL bit
in the TXCTRL register controls the polarity of TOUT+
and TOUT- vs. TIN+ and TIN-. The SET_PWCTRL regis-
ter controls the output eye-crossing adjustment. A sta-
tus indicator bit (TXED) monitors the presence of an AC
input signal.
Table 2. Slew-Rate Control for CML
RX_EN
SQ_EN
LOS
OPERATION MODE
DESCRIPTION
Output Stage
RATE_SEL
OPERATION MODE DESCRIPTION
0
1
1
1
X
0
1
1
X
X
0
1
CML output disabled.
CML output enabled.
CML output enabled.
CML output disabled.
0
1
1.25Gbps operation with reduced output
edge speed.
Up to 10.32Gbps operation.
16
Maxim Integrated
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