参数资料
型号: MAX3799ETJ+T
厂商: Maxim Integrated
文件页数: 7/36页
文件大小: 0K
描述: IC AMP LIMITING VCSEL DVR 32TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: 激光二极管驱动器
数据速率: 14Gbps
通道数: 1
电源电压: 2.85 V ~ 3.63 V
电流 - 电源: 97mA
电流 - 调制: 12mA
电流 - 偏置: 15mA
工作温度: -40°C ~ 85°C
封装/外壳: 32-WFQFN 裸露焊盘
供应商设备封装: 32-TQFN-EP(5x5)
包装: 带卷 (TR)
安装类型: 表面贴装
MAX3799
1Gbps to 14Gbps, SFP+ Multirate Limiting
Amplifier and VCSEL Driver
ELECTRICAL CHARACTERISTICS (continued)
(V CC = 2.85V to 3.63V, T A = -40°C to +85°C, CML receiver output load is AC-coupled to differential 100 ? , C AZ = 1nF, transmitter out-
put load is AC-coupled to differential 100 ? (see Figure 1), typical values are at +25°C, V CC = 3.3V, I BIAS = 6mA, I MOD = 6mA, unless
otherwise specified. Registers are set to default values unless otherwise noted, and the 3-wire interface is static during measure-
ments. For testing, the RATE_SEL bit was used and the RSEL pin was left open.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SDA Setup Time
SDA Hold Time
SCL Rise to SDA Propagation
Time
CSEL Pulse-Width Low
CSEL Leading Time Before the
First SCL Edge
CSEL Trailing Time After the
Last SCL Edge
t DS
t DH
t D
t CSW
t L
t T
500
100
100
5
500
500
ns
ns
ns
ns
ns
ns
SDA, SCL External Load
C B
Total bus capacitance on one line with
4.7k pullup to V CC
20
pF
Note 1: Supply current is measured with unterminated receiver CML output or with AC-coupled Rx output termination. The Tx out-
put and the bias current output must be connected to a separate supply to remove the modulation/bias current portion from
the supply current. BIAS must be connected to 2.0V. TOUT+/- must be connected through 50 ? load resistors to a separate
supply voltage.
Note 2: Guaranteed by design and characterization, T A = -40°C to +95°C.
Note 3: The data input transition time is controlled by a 4th-order Bessel filter with -3dB frequency = 0.75 x data rate. The determin-
istic jitter caused by this filter is not included in the DJ generation specifications.
Note 4: Test pattern is 00001111 at 1.25Gbps for RATE_SEL = 0. Test pattern is 00001111 at 8.5Gbps for RATE_SEL = 1.
Note 5: Receiver deterministic jitter is measured with a repeating 2 31 - 1 PRBS equivalent pattern at 10.32Gbps. For 1.25Gbps to
8.5Gbps, a repeating K28.5 pattern [00111110101100000101] is used. Deterministic jitter is defined as the arithmetic sum
of pulse-width distortion (PWD) and pattern-dependent jitter (PDJ).
Note 6: Measured with a k28.5 pattern from 1.0625Gbps to 8.5Gbps. Measured with 2 31 - 1 PRBS at 10.32Gbps.
Note 7: Measurement includes an input AC-coupling capacitor of 100nF and C CAZ of 100nF. The signal at the input is switched
between two amplitudes: Signal_ON and Signal_OFF.
1) Receiver operates at sensitivity level plus 1dB power penalty.
a) Signal_OFF = 0
Signal_ON = (+8dB) + 10log(min_assert_level)
b) Signal_ON = (+1dB) + 10log(max_deassert_level)
Signal_OFF = 0
2) Receiver operates at overload.
Signal_OFF = 0
Signal_ON = 1.2V P-P
max_deassert_level and the min_assert_level are measured for one LOS_THRESHOLD setting.
Note 8: Gain stability is defined as [(I_measured) - (I_reference)]/(I_reference) over the listed current range, temperature, and V CC
from +2.95V to +3.63V. Reference current measured at V CC = +3.2V, T A = +25°C.
Note 9: Transmitter deterministic jitter is measured with a repeating 2 7 - 1 PRBS, 72 0s, 2 7 - 1 PRBS, and 72 1s pattern at
10.32Gbps. For 1.0625Gbps to 8.5Gbps, a repeating K28.5 pattern [00111110101100000101] is used. Deterministic jitter is
defined as the arithmetic sum of PWD and PDJ.
Note 10: Gain stability is defined as [(I_measured) - (I_reference)]/(I_reference) over the listed current range, temperature, and V CC
from +2.85V to +3.63V. Reference current measured at V CC = +3.3V, T A = +25°C.
Maxim Integrated
7
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