参数资料
型号: MAX5099ATJ+T
厂商: Maxim Integrated Products
文件页数: 11/27页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ DL 32TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: 降压(降压)
输出类型: 可调式
输出数: 2
输出电压: 0.8 V ~ 17.1 V
输入电压: 4.5 V ~ 19 V
PWM 型: 电压模式
频率 - 开关: 200kHz ~ 2.2MHz
电流 - 输出: 1A,2A
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 32-WFQFN 裸露焊盘
包装: 带卷 (TR)
供应商设备封装: 32-TQFN-EP(5x5)
Dual, 2.2MHz, Automotive Synchronous Buck
Converter with 80V Load-Dump Protection
Pin Description
PIN
1, 32
2, 3
4
5
6
7
8
9
10
11
12
13
14
NAME
SOURCE2
DRAIN2
PGOOD2
EN2
FB2
COMP2
OSC
SYNC
GATE
ON/OFF
IN_HIGH
V+
V L
FUNCTION
Converter 2 Internal MOSFET Source Connection. For buck converter operation, connect SOURCE2 to the
switched side of the inductor. For boost operation, connect SOURCE2 to PGND (Figure 5).
Converter 2 Internal MOSFET Drain Connection. For buck converter operation, use the MOSFET as a high-
side switch and connect DRAIN2 to the DC-DC converters supply input rail. For boost converter operation,
use the MOSFET as a low-side switch and connect DRAIN2 to the inductor and diode junction (Figure 5).
Converter Open-Drain Power-Good Output. PGOOD2 goes low when converter 2’s output falls below 92.5%
of its set regulation voltage. Use PGOOD2 and EN1 to sequence the converters.
Converter 2 Active-High Enable Input. Connect to V L for always-on operation.
Converter 2 Feedback Input. Connect FB2 to a resistive divider between converter 2’s output and SGND to
adjust the output voltage. To set the output voltage below 0.8V, connect FB2 to a resistive voltage-divider
from BYPASS to regulator 2’s output (Figure 2). See the Setting the Output Voltage section.
Converter 2 Internal Transconductance Amplifier Output. See the Compensation section.
Oscillator Frequency Set Input. Connect a resistor from OSC to SGND (R OSC ) to set the switching frequency
(see the Setting the Switching Frequency section). Set R OSC for an oscillator frequency equal to the SYNC
input frequency when using external synchronization. R OSC is still required when an external clock is
connected to the SYNC input. See the Synchronization (SYNC) section.
External Clock Synchronization Input. Connect SYNC to a 400kHz to 4400kHz clock to synchronize the
switching frequency with the system clock. Each converter frequency is 1/2 of the frequency applied to
SYNC (FSEL_1 = V L ). For FSEL_1 = SGND, the switching frequency of converter 1 becomes 1/4 of the
SYNC frequency. Connect SYNC to SGND when not used.
Gate Drive Output. Connect to the gate of the external n-channel load-dump protection MOSFET. GATE =
IN_HIGH + 9V (typ) with IN_HIGH = 12V. GATE pulls to IN_HIGH by an internal n-channel MOSFET when V+
raises 2V above IN_HIGH. Leave GATE unconnected if the load-dump protection is not used (MOSFET not
installed).
n-Channel Switch Enable Input. Drive ON/OFF high for normal operation. Drive ON/OFF low to turn off the
external n-channel load-dump protection MOSFET and reduce the supply current to 7μA (typ). When
ON/OFF is driven low, both DC-DC converters are disabled and the PGOOD_ outputs are driven low.
Connect to V+ if the external load-dump protection is not used (MOSFET not installed).
Startup Input. IN_HIGH is protected by internally clamping to 21V (max). Connect a resistor (4k Ω max) from
IN_HIGH to the drain of the protection switch. Bypass IN_HIGH with a 4.7μF electrolytic or 1μF minimum
ceramic capacitor. Connect to V+ if the external load-dump protection is not used (MOSFET not installed).
Input Supply Voltage. V+ can range from 5.2V to 19V. Connect V+, IN_HIGH, and V L together for 4.5V to
5.5V input operation. Bypass V+ to SGND with a 1μF minimum ceramic capacitor.
Internal Regulator Output. The V L regulator is used to supply the drive current at input VDRV. When driving
VDRV, use an RC lowpass filter to decouple switching noise from VDRV to the V L regulator (see the Typical
Application Circuit ). Bypass V L to SGND with a 4.7μF minimum ceramic capacitor.
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11
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