参数资料
型号: MAX5099ATJ+T
厂商: Maxim Integrated Products
文件页数: 23/27页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ DL 32TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: 降压(降压)
输出类型: 可调式
输出数: 2
输出电压: 0.8 V ~ 17.1 V
输入电压: 4.5 V ~ 19 V
PWM 型: 电压模式
频率 - 开关: 200kHz ~ 2.2MHz
电流 - 输出: 1A,2A
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 32-WFQFN 裸露焊盘
包装: 带卷 (TR)
供应商设备封装: 32-TQFN-EP(5x5)
Dual, 2.2MHz, Automotive Synchronous Buck
Converter with 80V Load-Dump Protection
2) Place a zero f Z 1 =
1
2 π × R F × C F
at 0 . 75 × f LC .
Choose a suitable power MOSFET that can safely oper-
ate in the saturation region. Verify its capability to sup-
port the downstream DC-DC converters’ input current
during the load-dump event by checking its safe oper-
C F =
1
2 π × 0 . 75 × f LC × R F
ating area (SOA) characteristics.
Since the transient peak power dissipation on the
MOSFET can be very high during the load-dump event,
V OSC ? ? ( ) + ω C O O ? ?
?
?
ω C F IN
C I =
where R F ≥ 10kΩ.
3) Calculate C I for a target crossover frequency, f C :
2 2
1 ? D L C
R V
where ω C = 2 π x f C .
also refer to the thermal impedance graph given in the
data sheet of the power MOSFET to make sure its tran-
sient power dissipation is kept within the recommended
limits.
Improving Noise Immunity
In applications where the MAX5099 is subject to noisy
environments, adjust the controller’s compensation to
improve the system’s noise immunity. In particular, high-
4) Place a pole f P 1 =
1
2 π × R I × C I
at f ZERO , RHP
frequency noise coupled into the feedback loop causes
jittery duty cycles. One solution is to lower the crossover
frequency (see the Compensation section).
or 5 x f C , whichever is lower.
R I =
1
2 π × f × C I
V L
5) Place the second zero f Z 2 =
1
2 π × R 1 × C I
at f LC .
MAX5099
R 1 =
1
2 π × f LC × C I
? R I
VDRV
BST_/VDD_
6) Place the second pole at 1/2 the switching frequency.
PGND
V+
C CF =
C F
( 2 π × 0 . 5 × f SW × R F × C F ) ? 1
DRAIN_
VOUT_
Load-Dump Protection MOSFET
Select the external MOSFET with an adequate voltage
rating, V DSS , to withstand the maximum expected load-
dump input voltage. The on-resistance of the MOSFET,
R DS(ON) , should be low enough to maintain a minimal
voltage drop at full load, limiting the power dissipation
of the MOSFET.
During regular operation, the power dissipated by the
DRAIN_
*DL_
SOURCE_
SOURCE_
SGND
C OUT
MOSFET is:
P NORMAL = I LOAD2 x R DS(ON)
FB_
where I LOAD is equal to the sum of both converters’
input currents.
The MOSFET operates in a saturation region during
load dump, with both high voltage and current applied.
*LEAVE DL_ UNCONNECTED.
Figure 5. Boost Application
______________________________________________________________________________________
23
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