参数资料
型号: MAX5099ATJ+T
厂商: Maxim Integrated Products
文件页数: 24/27页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ DL 32TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: 降压(降压)
输出类型: 可调式
输出数: 2
输出电压: 0.8 V ~ 17.1 V
输入电压: 4.5 V ~ 19 V
PWM 型: 电压模式
频率 - 开关: 200kHz ~ 2.2MHz
电流 - 输出: 1A,2A
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 32-WFQFN 裸露焊盘
包装: 带卷 (TR)
供应商设备封装: 32-TQFN-EP(5x5)
Dual, 2.2MHz, Automotive Synchronous Buck
Converter with 80V Load-Dump Protection
PCB Layout Guidelines
Careful PCB layout is critical to achieve low switching
losses and clean, stable operation. This is especially
true for dual converters where one channel can affect
the other. Refer to the MAX5098A/MAX5099 Evaluation
Kit data sheet for a specific layout example. Use a mul-
tilayer board whenever possible for better noise immu-
nity. Follow these guidelines for good PCB layout:
1) For SGND, use a large copper plane under the IC
and solder it to the exposed paddle. To effectively
use this copper area as a heat exchanger between
the PCB and ambient, expose this copper area on
the top and bottom side of the PCB. Do not make a
direct connection from the exposed pad copper
plane to SGND underneath the IC.
2) Isolate the power components and high-current
path from the sensitive analog circuitry.
3) Keep the high-current paths short, especially at the
ground terminals. This practice is essential for sta-
ble, jitter-free operation.
4) Connect SGND and PGND together at a single
point. Do not connect them together anywhere else
(refer to the MAX5099 Evaluation Kit data sheet for
more information).
5) Keep the power traces and load connections short.
This practice is essential for high efficiency. Use
thick copper PCBs (2oz vs. 1oz) to enhance full-
load efficiency.
6) Ensure that the feedback connection to C OUT is
short and direct.
7) Route high-speed switching nodes (BST_/VDD_,
SOURCE_) away from the sensitive analog areas
(BYPASS, COMP_, and FB_). Use the internal PCB
layer for SGND as an EMI shield to keep radiated
noise away from the IC, feedback dividers, and
analog bypass capacitors.
Layout Procedure
1) Place the power components first, with ground ter-
minals adjacent (inductor, C IN_ , and C OUT_ ). Make
all these connections on the top layer with wide,
copper-filled areas (2oz copper recommended).
2) Group the gate-drive components (bootstrap
diodes and capacitors, and V L bypass capacitor)
together near the controller IC.
3) Make the DC-DC controller ground connections as
follows:
a) Create a signal ground plane underneath the IC.
b) Connect this plane to SGND and use this plane
for the ground connection for the reference
(BYPASS), enable, compensation components,
feedback dividers, and OSC resistor.
c) Connect SGND and PGND together (this is the
only connection between SGND and PGND).
Refer to the MAX5098A/MAX5099 Evaluation Kit
data sheet for more information.
24
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