参数资料
型号: MAX8643ETG+T
厂商: Maxim Integrated Products
文件页数: 10/16页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 3A 24TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 0.6 V ~ 3.2 V
输入电压: 2.35 V ~ 3.6 V
PWM 型: 电压模式
频率 - 开关: 500kHz ~ 2MHz
电流 - 输出: 3A
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 24-WFQFN 裸露焊盘
包装: 带卷 (TR)
供应商设备封装: 24-TQFN-EP(4x4)
3A, 2MHz Step-Down Regulator
with Integrated Switches
Current Limit
The internal, high-side MOSFET has a typical 5.5A
peak current-limit threshold. When current flowing out
of LX exceeds this limit, the high-side MOSFET turns off
and the synchronous rectifier turns on. The synchro-
nous rectifier remains on until the inductor current falls
below the low-side current limit. This lowers the duty
cycle and causes the output voltage to droop until the
current limit is no longer exceeded. The MAX8643 uses
a hiccup mode to prevent overheating during short-cir-
cuit output conditions.
During current limit if V FB drops below 420mV and
stays below this level for 12μs or more, the part enters
hiccup mode. The high-side MOSFET and the synchro-
nous rectifier are turned off and both COMP and REFIN
are internally pulled low. If REFIN and SS are connect-
ed together, then both are pulled low. The part remains
in this state for 1024 clock cycles and then attempts to
restart for 128 clock cycles. If the fault-causing current
limit has cleared, the part resumes normal operation.
Undervoltage Lockout (UVLO)
The UVLO circuitry inhibits switching when V DD is
below 2V (typ). Once V DD rises above 2V (typ), UVLO
clears and the soft-start function activates. A 100mV
hysteresis is built in for glitch immunity.
BST
The gate-drive voltage for the high-side, n-channel
switch is generated by a flying-capacitor boost circuit.
The capacitor between BST and LX is charged from the
V IN supply while the low-side MOSFET is on. When the
low-side MOSFET is switched off, the voltage of the
capacitor is stacked above LX to provide the necessary
turn-on voltage for the high-side internal MOSFET.
Frequency Select (FREQ)
The switching frequency is resistor programmable from
500kHz to 2MHz. Set the switching frequency of the IC
with a resistor (R FREQ ) connected from FREQ to GND.
R FREQ is calculated as:
Otherwise, the part reenters hiccup mode again.
Soft-Start and REFIN
R FREQ =
50 k Ω
0 . 95 μ s
× (
1
f S
? 0 . 05 μ s )
The MAX8643 utilizes an adjustable soft-start function
to limit inrush current during startup. An 8μA (typ) cur-
rent source charges an external capacitor connected to
SS. The soft-start time is adjusted by the value of the
external capacitor from SS to GND. The required
capacitance value is determined as:
where f S is the desired switching frequency in Hz.
Power-Good Output (PWRGD)
PWRGD is an open-drain output that goes high imped-
ance when V FB is above 0.9 x V REFIN . PWRGD pulls
low when V FB is below 90% of its regulation for at least
C =
8 μ A × t SS
0 . 6 V
48 clock cycles. PWRGD is low during shutdown.
Programming the Output Voltage
(CTL1, CTL2)
where t SS is the required soft-start time in seconds. The
MAX8643 also features an external reference input
(REFIN). The IC regulates FB to the voltage applied to
REFIN. The internal soft-start is not available when
using an external reference. A method of soft-start
when using an external reference is shown in Figure 2.
Connect REFIN to SS to use the internal 0.6V reference.
As shown in Table 1, the output voltage is pin program-
mable by the logic states of CTL1 and CTL2. CTL1 and
CTL2 are tri-level inputs: V DD , unconnected, and GND.
Table 1. CTL1 and CTL2 Output Voltage
Selection
CTL1
GND
CTL2
GND
V OUT (V)
0.6
R1
REFIN
V DD
GND
GND
V DD
Unconnected
V DD
0.7
0.8
1.0
R2
C
MAX8643
Unconnected
GND
1.2
Unconnected
Unconnected
V DD
Unconnected
V DD
GND
1.5
1.8
2.0
Figure 2. Typical Soft-Start Implementation with External
Reference
V DD
Unconnected
2.5
10
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