参数资料
型号: MAX8643ETG+T
厂商: Maxim Integrated Products
文件页数: 11/16页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 3A 24TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 0.6 V ~ 3.2 V
输入电压: 2.35 V ~ 3.6 V
PWM 型: 电压模式
频率 - 开关: 500kHz ~ 2MHz
电流 - 输出: 3A
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 24-WFQFN 裸露焊盘
包装: 带卷 (TR)
供应商设备封装: 24-TQFN-EP(4x4)
3A, 2MHz Step-Down Regulator
with Integrated Switches
The logic states of CTL1 and CTL2 should be pro-
grammed only before power-up. Once the part is
enabled, CTL1 and CTL2 should not be changed. If the
output voltage needs to be reprogrammed, cycle
power or EN and reprogram before enabling.
Shutdown Mode
Drive EN to GND to shut down the IC and reduce quies-
cent current to less than 12μA. During shutdown, the LX
is high impedance. Drive EN high to enable the
MAX8643.
put ripple occurs due to variations in the charge stored
in the output capacitor, the voltage drop due to the
capacitor ’s ESR, and the voltage drop due to the
capacitor’s ESL. Calculate the output voltage ripple
due to the output capacitance, ESR, and ESL:
V RIPPLE = V RIPPLE ( C ) +
V RIPPLE ( ESR ) + V RIPPLE ( ESL )
where the output ripple due to output capacitance,
ESR, and ESL is:
Thermal Protection
Thermal-overload protection limits total power dissipation
in the device. When the junction temperature exceeds T J
V RIPPLE ( C ) =
I P ? P
8 x C OUT x f S
V RIPPLE ( ESL ) = P ? P x ESL
V RIPPLE ( ESL ) = P ? P x ESL
I P ? P = IN OUT x OUT
L =
= +165°C, a thermal sensor forces the device into shut-
down, allowing the die to cool. The thermal sensor turns
the device on again after the junction temperature cools
by 20°C, causing a pulsed output during continuous
overload conditions. The soft-start sequence begins after
recovery from a thermal-shutdown condition.
Applications Information
IN and V DD Decoupling
To decrease the noise effects due to the high switching
frequency and maximize the output accuracy of
the MAX8643, decouple V IN with a 22μF capacitor from
V IN to PGND. Also decouple V DD with a 1μF from V DD
to GND. Place these capacitors as close to the IC
as possible.
Inductor Selection
Choose an inductor with the following equation:
V OUT × ( V IN ? V OUT )
f S × V IN × LIR × I OUT ( MAX )
where LIR is the ratio of the inductor ripple current to full
load current at the minimum duty cycle. Choose LIR
between 20% to 40% for best performance and stability.
Use an inductor with the lowest possible DC resistance
that fits in the allotted dimensions. Powdered iron ferrite
core types are often the best choice for performance.
With any core material, the core must be large enough
not to saturate at the current limit of the MAX8643.
Output-Capacitor Selection
The key selection parameters for the output capacitor are
capacitance, ESR, ESL, and voltage-rating requirements.
These affect the overall stability, output ripple voltage,
and transient response of the DC-DC converter. The out-
V RIPPLE ( ESR ) = I P ? P x ESR
I
t ON
I
t OFF
or whichever is larger.
The peak inductor current (I P-P ) is:
V ? V V
f S × L V IN
Use these equations for initial capacitor selection.
Determine final values by testing a prototype or an
evaluation circuit. A smaller ripple current results in less
output voltage ripple. Since the inductor ripple current
is a factor of the inductor value, the output voltage rip-
ple decreases with larger inductance. Use ceramic
capacitors for low ESR and low ESL at the switching
frequency of the converter. The ripple voltage due to
ESL is negligible when using ceramic capacitors.
Load-transient response depends on the selected out-
put capacitance. During a load transient, the output
instantly changes by ESR x Δ I LOAD . Before the con-
troller can respond, the output deviates further,
depending on the inductor and output capacitor val-
ues. After a short time, the controller responds by regu-
lating the output voltage back to its predetermined
value. The controller response time depends on the
closed-loop bandwidth. A higher bandwidth yields a
faster response time, preventing the output from deviat-
ing further from its regulating value. See the Compen-
sation Design section for more details.
______________________________________________________________________________________
11
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