参数资料
型号: MAX8643ETG+T
厂商: Maxim Integrated Products
文件页数: 7/16页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 3A 24TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 0.6 V ~ 3.2 V
输入电压: 2.35 V ~ 3.6 V
PWM 型: 电压模式
频率 - 开关: 500kHz ~ 2MHz
电流 - 输出: 3A
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 24-WFQFN 裸露焊盘
包装: 带卷 (TR)
供应商设备封装: 24-TQFN-EP(4x4)
3A, 2MHz Step-Down Regulator
with Integrated Switches
Pin Description
PIN
1, 7
2
3, 4
5
6
8
9
10
11
12
13
14, 15, 16
17–20
21, 22, 23
24
NAME
GND
V DD
CTL1,
CTL2
REFIN
SS
COMP
FB
OUT
FREQ
PWRGD
BST
LX
PGND
IN
EN
EP
FUNCTION
Analog Circuit Ground
Supply Voltage and Bypass Input. Connect V DD to IN with a 10 Ω resistor. Connect a 1μF ceramic
capacitor from V DD to GND.
Preset Output Voltage Selection Input. CTL1 and CTL2 set the output voltage to one of nine preset
voltages. See Table 1 for preset voltages.
External Reference Input. Connect REFIN to SS to use the internal 0.6V reference. Connecting REFIN to an
external reference voltage forces FB to regulate the voltage applied to REFIN. REFIN is internally pulled to
GND when the IC is in shutdown mode.
Soft-Start Input. Connect a capacitor from SS to GND to set the startup time. See the Soft-Start and REFIN
section for details on setting the soft-start time.
Output of the Voltage-Error Amplifier. Connect the necessary compensation network from COMP to FB.
COMP is internally pulled to GND when the IC is in shutdown mode.
Feedback Input. Connect FB to the center tap of an external resistor-divider from the output to GND to set
the output voltage from 0.6V to 90% of V IN . Connect FB through an RC network to the output when using
CTL1 and CTL2 to select any of nine preset voltages.
Output Voltage Sense. Connect to the output. Leave OUT unconnected when an external resistor-divider
is used.
Oscillator Frequency Selection. Connect a resistor from FREQ to GND to select the switching frequency.
Power-Good Output. Open-drain output that is high impedance when V FB ≥ 90% of V REFIN or 0.6V. PWRGD is
internally pulled low when V FB falls below 90% of its regulation point. PWRGD is internally pulled low when the
IC is in shutdown mode, V DD or V IN is below the UVLO threshold, or the IC is in thermal shutdown.
High-Side MOSFET Driver Supply. Bypass BST to LX with a 0.1μF capacitor.
Inductor Connection. All LX pins are internally connected together. Connect all LX pins to the output
inductor. LX is high impedance when the IC is in shutdown mode.
Power Ground. Connect all PGND pins externally to the power ground plane.
Power-Supply Input. Input supply range is from 2.35V to 3.6V. Bypass with 22μF ceramic capacitance to
PGND externally. See the Typical Application Circuit .
Enable Input. Logic input to enable/disable the MAX8643.
Exposed Paddle. Connect to a large ground plane to optimize thermal performance.
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