参数资料
型号: MAX8643ETG+T
厂商: Maxim Integrated Products
文件页数: 12/16页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 3A 24TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 0.6 V ~ 3.2 V
输入电压: 2.35 V ~ 3.6 V
PWM 型: 电压模式
频率 - 开关: 500kHz ~ 2MHz
电流 - 输出: 3A
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 24-WFQFN 裸露焊盘
包装: 带卷 (TR)
供应商设备封装: 24-TQFN-EP(4x4)
3A, 2MHz Step-Down Regulator
with Integrated Switches
C IN _ MIN =
Input-Capacitor Selection
The input capacitor reduces the current peaks drawn
from the input power supply and reduces switching
noise in the IC. The total input capacitance must be
equal to or greater than the value given by the following
equation to keep the input ripple voltage within specs
and minimize the high-frequency ripple current being
fed back to the input source:
D x t S x I OUT
V IN ? RIPPLE
where V IN-RIPPLE is the maximum allowed input ripple
voltage across the input capacitors and is recommend-
ed to be less than 2% of the minimum input voltage. D
is the duty cycle (V OUT / V IN ), and t S is the switching
period (1/f S ).
The impedance of the input capacitor at the switching
frequency should be less than that of the input source so
parallel, the value of the ESR in the above equation is
equal to that of the ESR of a single output capacitor
divided by the total number of output capacitors.
The high switching frequency range of the MAX8643
allows the use of ceramic output capacitors. Since the
ESR of ceramic capacitors is typically very low, the fre-
quency of the associated transfer function zero is higher
than the unity-gain crossover frequency, f C , and the zero
cannot be used to compensate for the double pole creat-
ed by the output filtering inductor and capacitor. The dou-
ble pole produces a gain drop of 40dB/decade and a
phase shift of 180°/decade. The error amplifier must com-
pensate for this gain drop and phase shift to achieve a
stable high-bandwidth closed-loop system. Therefore,
use type III compensation as shown in Figure 3 and
Figure 4. Type III compensation possesses three poles
and two zeros with the first pole, f P1_EA , located at zero
frequency (DC). Locations of other poles and zeros of the
type III compensation are given by:
high-frequency switching currents do not pass through
the input source but are instead shunted through the
input capacitor. High source impedance requires high
input capacitance. The input capacitor must meet the
f Z 1 _ EA =
1
2 π x R 1 x C 1
ripple current requirement imposed by the switching cur-
rents. The RMS input ripple current is given by:
LX
L
V OUT
I RIPPLE = I LOAD ×
V OUT × (V IN ? V OUT )
V IN
MAX8643
OUT
C OUT
R3
R2
C3
where I RIPPLE is the input RMS ripple current.
Compensation Design
CTL1
CTL2
FB
COMP
R1
C1
R4
The power transfer function consists of one double pole
and one zero. The double pole is introduced by the out-
put filtering inductor, L, and the output filtering capacitor,
C O . The ESR of the output filtering capacitor determines
C2
a) EXTERNAL RESISTOR-DIVIDER
f P 1 _ LC = f P 2 _ LC =
2 π x L x C O x ? O
? R O + R L ?
the zero. The double pole and zero frequencies are
given as follows:
1
? R + ESR ?
?
1
f Z _ ESR =
2 π x ESR x C O
MAX8643
R3
8k Ω
LX
OUT
L
C OUT
V OUT
R2
C3
where R L is equal to the sum of the output inductor’s
DCR and the internal switch resistance, R DSON . A typical
value for R DSON is 37m Ω . R O is the output load resis-
tance, which is equal to the rated output voltage divided
VOLTAGE
SELECT
CTL1
CTL2
FB
COMP
R1
C2
C1
by the rated output current. ESR is the total equivalent
series resistance of the output filtering capacitor. If there
is more than one output capacitor of the same type in
b) INTERNAL PRESET VOLTAGE
Figure 3. Type III Compensation Network
12
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