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参数资料
| 型号： | MAX8660AETL+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 21/44页 |
| 文件大小： | 0K |
| 描述： | IC POWER MANAGE XSCALE 40-TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 60 |
| 应用： | 处理器 |
| 电源电压： | 2.6 V ~ 6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-WFQFN 裸露焊盘 |
| 供应商设备封装： | 40-TQFN-EP（5x5） |
| 包装： | 管件 |
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High-Efficiency, Low-I Q , PMICs with Dynamic
Voltage Management for Mobile Applications
Pin Description (continued)
PIN
MAX8660 MAX8661
NAME
FUNCTION
REG2 Enable Input. Drive EN2 high to turn on REG2. EN2 has hysteresis so that an RC can be
32
32
EN2
used to implement manual sequencing with respect to other inputs. EN2 is typically driven by the
SYS_EN output of an Marvell PXA3xx processor.
Serial-Address Input. Connect SRAD to AGND for a 7-bit slave address of 0110 100 (0x68).
33
33
SRAD
Connect SRAD to IN to change the address to 0110 101 (0x6A). The eighth slave address bit is
always zero since the MAX8660/MAX8661 are write-only. See the Slave Address section for more
information.
34
—
35
—
36
—
—
34
—
35
—
36
PG1
GND
LX1
N.C.
PV1
PV
REG1 Power Ground. Connect PG1, PG2, PG3, PG4, and AGND together. Refer to the MAX8660 EV
kit data sheet for more information.
Ground. Connect all GND pins to EP.
REG1 Switching Node. Connect LX1 to the REG1 inductor. LX1 is high impedance when REG1 is
shutdown.
No Internal Connection
REG1 Power Input. Connect a 4.7μF ceramic capacitor from PV1 to PG1. All PV pins and IN must
be connected together externally.
Power Input. All PV pins and IN must be connected together externally.
REG1 Enable Input. Drive EN1 high to turn on REG1. EN1 has hysteresis so that an RC can be
37
—
EN1
used to implement manual sequencing with respect to other inputs. EN1 is typically driven by the
SYS_EN output of an applications processor.
—
37
GND
Ground. Connect all GND pins to EP.
REG1 Voltage Sense Input. Connect V1 directly to the REG1 output voltage. The output voltage of
38
—
V1
REG1 is selected by SET1. Connect V1 to VCC_IOx of the applications processor. V1 is internally
pulled to AGND through 650 ? when REG1 is shut down.
—
38
GND
Ground. Connect all GND pins to EP.
REG1 Voltage Select Input. SET1 is a tri-level logic input. Connect SET1 to select the V1 output
39
—
SET1
voltage as detailed in Table 3. The REG1 output voltage selected by SET1 is latched at the end of
the REG1 soft-start period. Changes to SET1 after the startup period have no effect.
—
39
GND
Ground. Connect all GND pins to EP.
REG4 Feedback Sense Input. Connect V4 directly to the REG4 output voltage. The REG4 output
40
40
V4
voltage is adjustable from 0.725V to 1.8V with the serial interface. V4 is internally pulled to AGND
through 550 ? when REG4 is shut down. V4 powers VCC_SRAM on the applications processor.
Exposed Pad. Connect the exposed pad to ground. Connecting the exposed pad to ground does
—
—
EP
not remove the requirement for proper ground connections to PG1, PG2, PG3, PG4, and AGND.
The exposed pad is attached with epoxy to the substrate of the die, making it an excellent path to
remove heat from the IC.
21
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MAX8660AETL+ | 功能描述:PMIC 解决方案 Low-IQ PMIC w/Dynamic V Mgt RoHS:否 制造商:Texas Instruments 安装风格:SMD/SMT 封装 / 箱体:QFN-24 封装:Reel |
| MAX8660AETL+T | 功能描述:PMIC 解决方案 Low-IQ PMIC w/Dynamic V Mgt RoHS:否 制造商:Texas Instruments 安装风格:SMD/SMT 封装 / 箱体:QFN-24 封装:Reel |
| MAX8660BETL+ | 功能描述:PMIC 解决方案 Low-IQ PMIC w/Dynamic V Mgt RoHS:否 制造商:Texas Instruments 安装风格:SMD/SMT 封装 / 箱体:QFN-24 封装:Reel |
| MAX8660BETL+T | 功能描述:PMIC 解决方案 Low-IQ PMIC w/Dynamic V Mgt RoHS:否 制造商:Texas Instruments 安装风格:SMD/SMT 封装 / 箱体:QFN-24 封装:Reel |
| MAX8660ETL/V+ | 功能描述:PMIC 解决方案 Low-IQ PMIC w/Dynamic V Mgt RoHS:否 制造商:Texas Instruments 安装风格:SMD/SMT 封装 / 箱体:QFN-24 封装:Reel |
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