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参数资料
| 型号： | MAX8660AETL+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 33/44页 |
| 文件大小： | 0K |
| 描述： | IC POWER MANAGE XSCALE 40-TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 60 |
| 应用： | 处理器 |
| 电源电压： | 2.6 V ~ 6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-WFQFN 裸露焊盘 |
| 供应商设备封装： | 40-TQFN-EP（5x5） |
| 包装： | 管件 |
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High-Efficiency, Low-I Q , PMICs with Dynamic
Voltage Management for Mobile Applications
where V LBOR is the rising voltage at the top of R1 (typi-
cally V IN ) when LBO goes high, and V LBOF is the falling
voltage at the top of R1 when LBO goes low.
For example, to set V LBOR to 3.6V and V LBOF to 3.2V,
choose R3 to be 1M ? . Then, R1 = 1.8M ? and
R2 = 80k ? .
If the low-battery-detector feature is not required, con-
nect LBO to ground and connect LBF and LBR to IN.
Internal Off-Discharge Resistors
Each regulator on the MAX8660/MAX8661 has an inter-
nal resistor that discharges the output capacitor when
the regulator is off (Table 8). The internal discharge
resistors pull their respective output to ground when the
regulator is off, ensuring that load circuitry always pow-
ers down completely. The internal off-discharge resis-
tors are active when a regulator is disabled, when the
device is in OVLO, and when the device is in UVLO
with V IN greater than 1.0V. With V IN less than 1.0V, the
internal off-discharge resistors may not activate.
Thermal-Overload Protection
Thermal-overload protection limits total power dissipa-
tion in the MAX8660/MAX8661. When internal thermal
sensors detect a die temperature in excess of +160 ° C,
the corresponding regulator(s) are shut down, allowing
the IC to cool. The regulators turn on again after the
junction cools by 15 ° C, resulting in a pulsed output dur-
ing continuous thermal-overload conditions.
A thermal overload on any of REG1 through REG5 only
shuts down the overloaded regulator. An overload on
REG6 or REG7 shuts down both regulators together.
During thermal overload, REG8 is not turned off, and
the I 2 C interface and voltage monitors remain active.
Table 8. Internal Off-Discharge Resistor
I 2 C Interface
An I 2 C-compatible, 2-wire serial interface controls a
variety of MAX8660/MAX8661 functions:
? The output voltages of V3–V7 are set by the serial
interface.
? Each of the four step-down DC-DC converters
(REG1–REG4) can be put into forced-PWM operation.
? REG3 and REG4 can be enabled by the serial inter-
face or by a hardware-enable pin (EN34). See the
REG3/REG4 Enable (EN34, EN3, EN4) section for
more information.
? REG6 and REG7 are activated only by the serial interface.
The serial interface operates whenever V IN is between
V UVLO (typically 2.40V) and V OVLO (typically 6.35V).
When V IN is outside the I 2 C operation range, the I 2 C
registers are reset to their default values.
The serial interface consists of a bidirectional serial-data
line (SDA) and a serial-clock input (SCL). The MAX8660/
MAX8661 are slave-only devices, relying upon a master
to generate a clock signal. The master (typically the
applications processor) initiates data transfer on the bus
and generates SCL to permit data transfer.
I 2 C is an open-drain bus. SDA and SCL require pullup
resistors (500 ? or greater). Optional resistors (24 ? ) in
series with SDA and SCL protect the device inputs from
high-voltage spikes on the bus lines. Series resistors also
minimize cross-talk and undershoot on bus signals.
The Marvell PXA3xx specification contains an extensive
list of registers for various functions, not all of which are
provided on the MAX8660/MAX8661. The list in Table 9 is
a subset of the Marvell list as it relates to functions includ-
ed in the PMIC. Even though the MAX8660/MAX8661 use
a subset of the specified registers, they acknowledge
writes to the entire register space (0x00 to 0xFF).
REGULATOR
REG1
REG2
REG3
REG4
REG5
REG6
REG7
REG8
INTERNAL OFF-DISCHARGE
RESISTOR VALUE
650 ? ±30%
650 ? ±30%
550 ? ±30%
550 ? ±30%
2k ? ±30%
350 ? ±30%
350 ? ±30%
1.5k ? ±30%
In Marvell PXA3xx applications, the pullups are typically
to VCC_IOx.
Data Transfer
One data bit is transferred during each SCL clock
cycle. The data on SDA must remain stable during the
high period of the SCL clock pulse. Changes in SDA
while SCL is high are control signals (see the START
and STOP Conditions section for more information).
Each transmit sequence is framed by a START (S) condi-
tion and a STOP (P) condition. Each data packet is 9 bits
long; 8 bits of data followed by the acknowledge bit. The
MAX8660/MAX8661 suport data transfer rates with SCL
frequencies up to 400kHz.
33
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MAX8660AETL+ | 功能描述:PMIC 解决方案 Low-IQ PMIC w/Dynamic V Mgt RoHS:否 制造商:Texas Instruments 安装风格:SMD/SMT 封装 / 箱体:QFN-24 封装:Reel |
| MAX8660AETL+T | 功能描述:PMIC 解决方案 Low-IQ PMIC w/Dynamic V Mgt RoHS:否 制造商:Texas Instruments 安装风格:SMD/SMT 封装 / 箱体:QFN-24 封装:Reel |
| MAX8660BETL+ | 功能描述:PMIC 解决方案 Low-IQ PMIC w/Dynamic V Mgt RoHS:否 制造商:Texas Instruments 安装风格:SMD/SMT 封装 / 箱体:QFN-24 封装:Reel |
| MAX8660BETL+T | 功能描述:PMIC 解决方案 Low-IQ PMIC w/Dynamic V Mgt RoHS:否 制造商:Texas Instruments 安装风格:SMD/SMT 封装 / 箱体:QFN-24 封装:Reel |
| MAX8660ETL/V+ | 功能描述:PMIC 解决方案 Low-IQ PMIC w/Dynamic V Mgt RoHS:否 制造商:Texas Instruments 安装风格:SMD/SMT 封装 / 箱体:QFN-24 封装:Reel |
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