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参数资料
| 型号： | MAX8660AETL+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 36/44页 |
| 文件大小： | 0K |
| 描述： | IC POWER MANAGE XSCALE 40-TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 60 |
| 应用： | 处理器 |
| 电源电压： | 2.6 V ~ 6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-WFQFN 裸露焊盘 |
| 供应商设备封装： | 40-TQFN-EP（5x5） |
| 包装： | 管件 |
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High-Efficiency, Low-I Q , PMICs with Dynamic
Voltage Management for Mobile Applications
Table 10. DVM Voltage-Change Register (VCC1, 0x20)
REGISTER
ADDRESS
REGISTER
NAME
BIT
NAME
FUNCTION
V5 ( VCC_MVT ) voltage select:
7
6
5
MVS
MGO
SVS
0—Ramp V5 to voltage selected by MDTV1 (default)
1—Ramp V5 to voltage selected by MDTV2
Start V5 ( VCC_MVT ) voltage change:
0—Hold V5 at current level (default)
1—Ramp V5 as selected by MVS
V4 ( VCC_SRAM ) voltage select:
0—Ramp V4 to voltage selected by SDTV1 (default)
1—Ramp V4 to voltage selected by SDTV2
0x20
VCC1
4
SGO
Start V4 ( VCC_SRAM ) voltage change:
0—Hold V4 at current level (default)
1—Ramp V4 as selected by SVS
3
2
1
0
R
R
AVS
AGO
Reserved
Reserved
V3 ( VCC_APPS ) voltage select:
0—Ramp V3 to voltage selected by ADTV1 (default)
1—Ramp V3 to voltage selected by ADTV2
Start V3 ( VCC_APPS ) voltage change:
0—Hold V3 at current level (default)
1—Ramp V3 as selected by AVS
I 2 C Write Operation
The MAX8660/MAX8661 are write-only devices and
recognize the “write byte” protocol as defined in the
SMBus specification and shown in section A of Figure
11. The “write byte ” protocol allows the I 2 C master
device to send 1 byte of data to the slave device. The
“write byte” protocol requires a register pointer address
for the subsequent write. The MAX8660/MAX8661
acknowledge any register pointer even though only a
subset of those registers actually exists in the device.
The “write byte” protocol is as follows:
1) The master sends a start command.
2) The master sends the 7-bit slave address followed
by a write bit.
3) The addressed slave asserts an acknowledge by
pulling SDA low.
4) The master sends an 8-bit register pointer.
5) The slave acknowledges the register pointer.
6) The master sends a data byte.
7) The slave updates with the new data.
8) The slave acknowledges the data byte.
9) The master sends a STOP condition.
In addition to the write-byte protocol, the MAX8660/
MAX8661 recognize the multiple byte register-data pair
protocol as shown in section B of Figure 11. This proto-
col allows the I 2 C master device to address the slave
only once and then send data to multiple registers in a
random order. Registers may be written continuously
until the master issues a STOP condition.
The multiple-byte register-data pair protocol is as
follows:
1) The master sends a start command.
2) The master sends the 7-bit slave address followed
by a write bit.
3) The addressed slave asserts an acknowledge by
pulling SDA low.
4) The master sends an 8-bit register pointer.
5) The slave acknowledges the register pointer.
6) The master sends a data byte.
7) The slave updates with the new data.
8) The slave acknowledges the data byte.
9) Steps 5 to 7 are repeated as many times as
the master requires. Registers may be accessed in
random order.
10)The master sends a STOP condition.
36
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MAX8660AETL+ | 功能描述:PMIC 解决方案 Low-IQ PMIC w/Dynamic V Mgt RoHS:否 制造商:Texas Instruments 安装风格:SMD/SMT 封装 / 箱体:QFN-24 封装:Reel |
| MAX8660AETL+T | 功能描述:PMIC 解决方案 Low-IQ PMIC w/Dynamic V Mgt RoHS:否 制造商:Texas Instruments 安装风格:SMD/SMT 封装 / 箱体:QFN-24 封装:Reel |
| MAX8660BETL+ | 功能描述:PMIC 解决方案 Low-IQ PMIC w/Dynamic V Mgt RoHS:否 制造商:Texas Instruments 安装风格:SMD/SMT 封装 / 箱体:QFN-24 封装:Reel |
| MAX8660BETL+T | 功能描述:PMIC 解决方案 Low-IQ PMIC w/Dynamic V Mgt RoHS:否 制造商:Texas Instruments 安装风格:SMD/SMT 封装 / 箱体:QFN-24 封装:Reel |
| MAX8660ETL/V+ | 功能描述:PMIC 解决方案 Low-IQ PMIC w/Dynamic V Mgt RoHS:否 制造商:Texas Instruments 安装风格:SMD/SMT 封装 / 箱体:QFN-24 封装:Reel |
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