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| 型号： | MAX8671XETL+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 20/44页 |
| 文件大小： | 0K |
| 描述： | IC PMIC W/CHARGER 40-TQFN-EP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 功能： | 充电管理 |
| 电池化学： | 锂离子（Li-Ion）、锂聚合物（Li-Pol） |
| 电源电压： | 4.1 V ~ 6.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-WFQFN 裸露焊盘 |
| 供应商设备封装： | 40-TQFN-EP（5x5） |
| 包装： | 带卷 (TR) |
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PMIC with Integrated Charger and
Smart Power Selector for Handheld Devices
Pin Description
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
NAME
USUS
DC
USB
FB5
PV5
OUT5
PG2
LX2
PV2
CEN
FB2
DOK
FB4
BP
OUT4
PV4
BVSET
AGND
FB1
EN
PWM
PV1
FUNCTION
USB Suspend Digital Input. As shown in Table 1, driving USUS high suspends the DC or USB inputs
if they are configured as a USB power input.
DC Power Input. DC is capable of delivering 1A to SYS. DC supports both AC adaptors and USB
inputs. As shown in Table 1, the DC current limit is controlled by PEN1, PEN2, USUS, and R DISET .
USB Power Input. USB is capable of delivering 0.5A to SYS. As shown in Table 1, the USB current
limit is controlled by PEN1, PEN2, and USUS.
Feedback Input for REG5. Connect FB5 to the center of a resistor voltage-divider from OUT5 to
AGND to set the REG5 output voltage from 0.6V to V PV5 .
Power Input for REG5. Connect PV5 to SYS, or a supply between 1.7V and V SYS . Bypass PV5 to
power ground with a 1μF ceramic capacitor.
Linear Regulator Power Output. OUT5 is internally pulled to AGND by 1k Ω in shutdown.
Power Ground for the REG2 Step-Down Regulator
Inductor Switching Node for REG2. LX2 is internally pulled to PG2 by 1k Ω in shutdown.
Power Input for the REG2 Step-Down Regulator. Connect PV2 to SYS. Bypass PV2 to PG2 with a
4.7μF ceramic capacitor.
Active-Low Charger Enable Input. Pull CEN low to enable the charger, or drive CEN high to disable
charging. The battery charger is also disabled when USUS is high.
Feedback Input for REG2. Connect FB2 to the center of a resistor voltage-divider from the REG2
output capacitors to AGND to set the output voltage from 1V to V SYS .
Active-Low, Open-Drain DC Power-OK Output. DOK is low when V DC is within its valid operating
range.
Feedback Input for REG4. Connect FB4 to the center of a resistor voltage-divider from the REG4
output capacitors to AGND to set the output voltage from 0.6V to V PV4 .
Reference Noise Bypass. Bypass BP with a low-leakage 0.01μF ceramic capacitor for reduced noise
on the LDO outputs.
Linear Regulator Power Output. OUT4 is internally pulled to AGND in shutdown.
Power Input for REG4. Connect PV4 to SYS, or a supply between 1.7V and V SYS . Bypass PV4 to
power ground with a 1μF ceramic capacitor.
Battery Regulation Voltage Set Node. Drive BVSET low to set the regulation voltage to 4.1V. Connect
BVSET to VL or leave unconnected to set the regulation voltage to 4.2V. Connect BVSET to AGND
through a 50k Ω resistor to set the regulation voltage to 4.350V.
Ground. AGND is the low-noise ground connection for the internal circuitry.
Feedback Input for REG1. Connect FB1 to the center of a resistor voltage-divider from the REG1
output capacitors to AGND to set the output voltage from 1V to V SYS .
Regulator Enable Input. Drive EN high to enable all regulator outputs. The sequencing is shown in
Figure 11. Drive EN low to disable the regulators.
Forced-PWM Input. Connect PWM high for forced-PWM operation on REG1, REG2, and REG3.
Connect PWM low for auto PWM operation. Do not change PWM on-the-fly. See the PWM section
for more information.
Power Input for the REG1 Step-Down Regulator. Connect PV1 to SYS. Bypass PV1 to PG1 with a
4.7μF ceramic capacitor.
20
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