参数资料
型号: MAX8671XETL+T
厂商: Maxim Integrated Products
文件页数: 39/44页
文件大小: 0K
描述: IC PMIC W/CHARGER 40-TQFN-EP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
功能: 充电管理
电池化学: 锂离子(Li-Ion)、锂聚合物(Li-Pol)
电源电压: 4.1 V ~ 6.6 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 40-WFQFN 裸露焊盘
供应商设备封装: 40-TQFN-EP(5x5)
包装: 带卷 (TR)
PMIC with Integrated Charger and
Smart Power Selector for Handheld Devices
USB/DC OVLO
Overvoltage lockout (OVLO) prevents an input supply
from being used when its voltage exceeds the operat-
ing range. Both USB and DC withstand input voltages
up to 14V. When the USB voltage is greater than the
USB OVLO threshold (6.9V typ), the USB input is dis-
connected from SYS, and UOK goes high impedance.
When the DC voltage is greater than the DC OVLO
threshold (6.9V typ), the DC input is disconnected from
SYS, and DOK goes high impedance. In addition, when
both DC and USB are in OVLO, the battery charger is
disabled, and BAT is connected to SYS through the
internal system load switch. REG1–REG4 are allowed to
operate from the battery when USB and DC are in over-
voltage lockout. The VL supply remains active in OVLO.
REG5 is intended to power the system USB transceiver
circuitry, which is only active when USB power is avail-
able. A valid source must be present on either the USB
or DC input for REG5 to enable.
SYS UVLO
A UVLO circuit monitors the voltage from SYS to
ground (V SYS ). When V SYS falls below V UVLO_SYS (2.5V
typ), REG1 –REG5 are disabled. V UVLO_SYS has a
100mV hysteresis. The VL supply remains active in SYS
UVLO.
REG4/REG5 UVLO
A UVLO circuit monitors the PV4 and PV5 LDO power
inputs. When the PV_ voltage is below 1.6V, it is invalid
and the LDO is disabled.
Thermal Limiting and Overload Protection
The MAX8671X is packaged in a 5mm x 5mm x 0.8mm
40-pin thin QFN. Table 7 shows the thermal character-
istics of this package. The MAX8671X has several
mechanisms to control junction temperature in the
event of a thermal overload.
Table 7. 5mm x 5mm x 0.8mm Thin QFN
Thermal Characteristics
Smart Power Selector Thermal-Overload Protection
The MAX8671X reduces the USB and DC current limits
by 5%/°C when the die temperature exceeds +100°C.
The system load (I SYS ) has priority over the charger
current, so input current is first reduced by lowering
charge current. If the junction temperature still reaches
+120°C in spite of charge-current reduction, no input
current is drawn from USB and DC; the battery supplies
the entire load and SYS is regulated 82mV (V BSREG )
below BAT. Note that this on-chip thermal-limiting cir-
cuit is not related to and operates independently from
the thermistor input.
Regulator Thermal-Overload Shutdown
The MAX8671X disables all regulator outputs (except
VL) when the junction temperature rises above +165°C,
allowing the device to cool. When the junction tempera-
ture cools by approximately 15°C, the regulators
resume the state indicated by the enable input (EN)
by repeating their soft-start sequence. Note that this
thermal-overload shutdown is a fail-safe mechanism;
proper thermal design should ensure that the junction
temperature of the MAX8671X never exceeds the
absolute maximum rating of +150°C.
Battery Charger Thermistor Input (THM)
The THM input connects to an external negative tem-
perature coefficient (NTC) thermistor to monitor battery
or system temperature. Charging is suspended when
the thermistor temperature is out of range. Additionally,
the charge timers are suspended and charge status
indicators report that the charger is in thermistor sus-
pend (CST[1:2] = 01). When the thermistor comes back
into range, charging resumes and the charge timer
continues from where it left off. Table 8 shows THM
temperature limits for various thermistor material con-
stants. If the battery temperature monitor is not
required, bias THM midway between V L and AGND
with a resistive divider—100k Ω ±5% resistors are rec-
ommended. Biasing THM midway between V L and
AGND bypasses this function.
SINGLE-LAYER PCB
MULTILAYER PCB
Continuous
Power
Dissipation
* θ JA
θ JC
1777.8mW
Derate 22.2mW/°C
above +70°C
45°C/W
1.7°C/W
2857.1mW
Derate 35.7mW/°C
above +70°C
28°C/W
1.7°C/W
* θ JA is specified according to the JESD51 standard.
______________________________________________________________________________________
39
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