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| 型号： | MAX8734AEEI+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 20/33页 |
| 文件大小： | 0K |
| 描述： | IC PWR SUPPLY CONTROLLER 28QSOP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 应用： | 电源控制器 |
| 输入电压： | 4.5 V ~ 24 V |
| 电流 - 电源： | 25µA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-QSOP |
| 供应商设备封装： | 28-QSOP |
| 包装： | 带卷 (TR) |
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High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
Reference and Linear Regulators
(REF, LDO5, and LDO3)
The 2V reference (REF) is accurate to ±1% over tem-
perature, making REF useful as a precision system
reference. Bypass REF to GND with a 0.22μF (min)
capacitor. REF can supply up to 100μA for external
loads. However, if extremely accurate specifications for
both the main output voltages and REF are essential,
avoid loading REF. Loading REF reduces the LDO5,
LDO3, OUT5, and OUT3 output voltages slightly
because of the reference load-regulation error.
Two internal regulators produce 5V (LDO5) and 3.3V
(LDO3). LDO5 provides gate drive for the external
MOSFETs and powers the PWM controller, logic, refer-
ence, and other blocks within the device. The LDO5
regulator supplies a total of 100mA for internal and
external loads, including MOSFET gate drive, which
typically varies from 10mA to 50mA, depending on
switching frequency and the external MOSFETs. LDO3
powers up when the reference (REF) is in regulation,
and supplies up to 100mA for external loads. Bypass
LDO5 and LDO3 with a minimum 4.7μF load; use an
additional 1μF per 5mA of internal and external load.
When the 5V main output voltage is above the LDO5
bootstrap-switchover threshold, an internal 1.4 ? p-chan-
nel MOSFET switch connects OUT5 to LDO5 while simul-
taneously shutting down the LDO5 linear regulator.
Similarly, when the 3.3V main output voltage is above the
LDO3 bootstrap-switchover threshold, an internal 1.5 ?
p-channel MOSFET switch connects OUT3 to LDO3 while
simultaneously shutting down the LDO3 linear regulator.
These actions bootstrap the device, powering the internal
circuitry and external loads from the output SMPS volt-
ages, rather than through linear regulators from the bat-
40 μ s (MAX)
INDUCTOR
CURRENT
tery. Bootstrapping reduces power dissipation due to
gate charge and quiescent losses by providing power
from a 90%-efficient switch-mode source, rather than
from a much-less-efficient linear regulator.
Current-Limit Circuit (ILIM_)
The current-limit circuit employs a “valley” current-sens-
ing algorithm. The MAX8734A uses the on-resistance of
the synchronous rectifier, while the MAX8732A/
MAX8733A use a discrete resistor in series with the
source of the synchronous rectifier as a current-sensing
element. If the magnitude of the current-sense signal at
CS_ (MAX8732A/MAX8733A)/LX_ (MAX8734A) is above
the current-limit threshold, the PWM is not allowed to initi-
ate a new cycle (Figure 7). The actual peak current is
greater than the current-limit threshold by an amount
equal to the inductor ripple current. Therefore, the exact
current-limit characteristic and maximum load capability
are a function of the current-limit threshold, inductor
value, and input and output voltage.
For the MAX8732A/MAX8733A, connect CS_ to the
junction of the synchronous rectifier source and a cur-
rent-sense resistor to GND. With a current-limit threshold
of 100mV, the accuracy is approximately ±7%. Using a
lower current-sense threshold results in less accuracy.
The current-sense resistor only dissipates power when
the synchronous rectifier is on.
For lower power dissipation, the MAX8734A uses the
on-resistance of the synchronous rectifier as the cur-
rent-sense element. Use the worst-case maximum
value for R DS(ON) from the MOSFET data sheet, and
add some margin for the rise in R DS(ON) with tempera-
ture. A good general rule is to allow 0.5% additional
resistance for each °C of temperature rise. The current
limit varies with the on-resistance of the synchronous
rectifier. The reward for this uncertainty is robust, loss-
less overcurrent sensing. When combined with the
-I PEAK
I LOAD
ZERO-CROSSING
0
I SONIC
DETECTION
I LIMIT
ON-TIME (t ON )
0
TIME
Figure 7. “Valley” Current-Limit Threshold Point
Figure 6. Ultrasonic Current Waveforms
20
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