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| 型号： | MAX8734AEEI+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 31/33页 |
| 文件大小： | 0K |
| 描述： | IC PWR SUPPLY CONTROLLER 28QSOP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 应用： | 电源控制器 |
| 输入电压： | 4.5 V ~ 24 V |
| 电流 - 电源： | 25µA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-QSOP |
| 供应商设备封装： | 28-QSOP |
| 包装： | 带卷 (TR) |
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High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
? Make all pin-strap control input connections ( SKIP ,
ILIM_, etc.) to GND or V CC of the device.
Layout Procedure
1) Place the power components first with ground ter-
minals adjacent (N2/N4 source, C IN_ , C OUT_ , D1
anode). If possible, make all these connections on
the top layer with wide, copper-filled areas.
2) Mount the controller IC adjacent to the synchronous-
rectifier MOSFETs, preferably on the back side to
keep DH_, GND, and the DL_ gate drive lines short
and wide. The DL_ gate trace must be short and
wide, measuring 50 mils to 100 mils wide if the
MOSFET is 1in from the controller device.
3) Group the gate-drive components (BST_ diode and
capacitor, V+ bypass capacitor) together near the
controller device.
4) Make the DC-DC controller ground connections as
follows: near the device, create a small analog
ground plane. Connect the small analog ground
plane to GND (Figure 13) and use the plane for the
ground connection for the REF and V CC bypass
capacitors, FB dividers, and ILIM resistors (if any).
Create another small ground island for PGND, and
use the plane for the V+ bypass capacitor, placed
very close to the device. Connect the AGND and
PGND planes together at the GND pin of the device.
5) On the board’s top side (power planes), make a
star ground to minimize crosstalk between the two
sides. The top-side star ground is a star connection
of the input capacitors and synchronous rectifiers.
Keep the resistance low between the star ground
and the source of the synchronous rectifiers for
accurate current limit. Connect the top-side star
ground (used for MOSFET, input, and output
capacitors) to the small island with a single short,
wide connection (preferably just a via).
Create PGND islands on the layer just below the
top-side layer (refer to the MAX1999 EV kit for an
example) to act as an EMI shield if multiple layers
are available (highly recommended). Connect each
of these individually to the star ground via, which
connects the top side to the PGND plane. Add one
more solid ground plane under the device to act as
an additional shield, and also connect the solid
ground plane to the star ground via.
6) Connect the output power planes (V CORE and system
ground planes) directly to the output filter capacitor
positive and negative terminals with multiple vias.
Table 5. MAX8732A/MAX8733A/MAX8734A and MAX1777/MAX1977/MAX1999 Differences
MAX8732A/MAX8733A/MAX8734A
Improved line transient behavior requires only
MAX1777/MAX1977/MAX1999
Line Transient Behavior
Ultrasonic Mode
LDO3 and LDO5 Sequencing
Soft-Shutdown Enable Delay
High-Output Impedance in UVLO
a 0.1μF filter capacitor on V+. Allows fast
rising-edge line transients of 10V/μs and
falling-edge line transients of 5V/μs.
Simplified Z pattern offers better efficiency
and smoother transition into continuous-
conduction mode.
LDO3 starts only after LDO5 is in regulation,
reducing the inrush current when SHDN goes
high.
Soft-shutdown (10 ? discharge feature) is
enabled immediately when an output is
enabled, and is not dependent on the 22ms
(typ) startup undervoltage blanking timer.
When LDO5 falls below its 4V (typ) UVLO
threshold, DH_ and DL_ are immediately
pulled low, and the outputs are high
impedance. The outputs are discharged by
the load.
A 4 ? /4.7μF filter capacitor is required on V+ to
limit the dV/dt on the V+ pin.
Original “W” pattern conducts through the high-
side MOSFET’s body diode, reducing efficiency.
Transition between ultrasonic mode and
continuous-conduction mode is not as smooth.
LDO3 and LDO5 start up together at the current
limit of each LDO, causing large inrush currents
through the 4 ? series resistor at V+.
Soft-shutdown (10 ? discharge feature) is
enabled only after the 22ms (typ) startup
undervoltage blanking time. This causes DL_ to
be driven high if the part is commanded to turn
off before the 22ms timer.
When LDO5 falls below its 4V (typ) UVLO
threshold, DH_ is immediately pulled low and
DL_ forced high to clamp the output rails. This
causes the outputs to swing below ground.
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