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| 型号： | MAX8734AEEI+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 30/33页 |
| 文件大小： | 0K |
| 描述： | IC PWR SUPPLY CONTROLLER 28QSOP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 应用： | 电源控制器 |
| 输入电压： | 4.5 V ~ 24 V |
| 电流 - 电源： | 25µA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-QSOP |
| 供应商设备封装： | 28-QSOP |
| 包装： | 带卷 (TR) |
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High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
USE AGND PLANE TO:
- BYPASS V CC AND REF
USE PGND PLANE TO:
- BYPASS LDO_
- TERMINATE EXTERNAL FB
- CONNECT PGND TO THE TOPSIDE STAR GROUND
VIA TO PGND
DIVIDER (IF USED)
- TERMINATE R ILIM
(IF USED)
- PIN-STRAP CONTROL
AGND
VIA BETWEEN POWER
AND ANALOG GROUND
VIA TO OUT5
OUT5
C3
GROUND
C4
OUT3
INPUTS
PGND
VIA TO OUT3
ANALOG GROUND
PLANE ON INNER LAYER
L1
N4
C1
C2
N2
L2
VIAS TO GROUND
VIA TO LX5
N3
V+
N1
VIA TO LX3
CONNECT PGND TO AGND
BENEATH THE CONTROLLER AT NOTE: EXAMPLE SHOWN IS FOR DUAL I.C. n-CHANNEL MOSFET.
ONE POINT ONLY AS SHOWN.
Figure 13. PC Board Layout Example
tion may be required on the secondary output to protect
any device connected to this output.
PC Board Layout Guidelines
Careful PC board layout is critical to achieve minimal
switching losses and clean, stable operation. This is
especially true when multiple converters are on the
same PC board where one circuit can affect the other.
The switching power stages require particular attention
(Figure 13). Refer to the MAX1999 EV kit I.C. data sheet
for a specific layout example.
Mount all of the power components on the top side of
the board with their ground terminals flush against one
another, if possible. Follow these guidelines for good
PC board layout:
? Isolate the power components on the top side from
the sensitive analog components on the bottom side
with a ground shield. Use a separate PGND plane
under the OUT3 and OUT5 sides (called PGND3 and
PGND5). Avoid the introduction of AC currents into
the PGND3 and PGND5 ground planes. Run the
power plane ground currents on the top side only, if
possible.
? Use a star ground connection on the power plane to
minimize the crosstalk between OUT3 and OUT5.
? Keep the high-current paths short, especially at the
ground terminals. This practice is essential for sta-
ble, jitter-free operation.
? Keep the power traces and load connections short.
This practice is essential for high efficiency. Using
thick copper PC boards (2oz vs. 1oz) can enhance
full-load efficiency by 1% or more. Correctly routing
PC board traces must be approached in terms of
fractions of centimeters, where a single milliohm of
excess trace resistance causes a measurable effi-
ciency penalty.
? CS_ (MAX8732A/MAX8733A)/LX_ (MAX8734A) and
GND connections to the synchronous rectifiers for
current limiting must be made using Kelvin-sense
connections to guarantee the current-limit accuracy.
With 8-pin SO MOSFETs, this is best done by routing
power to the MOSFETs from outside using the top
copper layer, while connecting CS_/LX_ traces inside
(underneath) the MOSFETs.
? When trade-offs in trace lengths must be made, it is
preferable to allow the inductor charging path to be
made longer than the discharge path. For example, it
is better to allow some extra distance between the
input capacitors and the high-side MOSFET than to
allow distance between the inductor and the syn-
chronous rectifier or between the inductor and the
output filter capacitor.
? Ensure that the OUT_ connection to C OUT_ is short and
direct. However, in some cases it may be desirable to
deliberately introduce some trace length between the
OUT_ connector node and the output filter capacitor
(see the Stability Considerations section).
? Route high-speed switching nodes (BST_, DH_, LX_,
and DL_) away from sensitive analog areas (REF,
ILIM_, and FB_). Use PGND3 and PGND5 as an EMI
shield to keep radiated switching noise away from the
IC’s feedback divider and analog bypass capacitors.
30
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