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参数资料
| 型号： | MAX8734AEEI+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 27/33页 |
| 文件大小： | 0K |
| 描述： | IC PWR SUPPLY CONTROLLER 28QSOP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 应用： | 电源控制器 |
| 输入电压： | 4.5 V ~ 24 V |
| 电流 - 电源： | 25µA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-QSOP |
| 供应商设备封装： | 28-QSOP |
| 包装： | 带卷 (TR) |
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High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
The maximum input capacitor RMS current for a single
SMPS is given by:
Generally, a small high-side MOSFET reduces switch-
ing losses at high input voltage. However, the R DS(ON)
(
? V OUT _ V + ? V OUT _
I RMS ≈ I LOAD ?
) ? ?
?
?
? V +
?
?
?
required to stay within package power-dissipation limits
often limits how small the MOSFET can be. The opti-
mum situation occurs when the switching (AC) losses
equal the conduction (R DS(ON) ) losses.
Switching losses in the high-side MOSFET can become
C OSS ( V IN ( MAX ) ) 2 f SW
When V+ = 2 x V OUT_ (D = 50%), I RMS has a maximum
current of I LOAD / 2.
The ESR of the input capacitor is important for deter-
mining capacitor power dissipation. All the power
(I RMS2 x ESR) heats up the capacitor and reduces effi-
ciency. Nontantalum chemistries (ceramic or OS-CON)
are preferred due to their low ESR and resilience to
power-up surge currents. Choose input capacitors that
exhibit less than +10°C temperature rise at the RMS
input current for optimal circuit longevity. Place the
drains of the high-side switches close to each other to
share common input bypass capacitors.
Power-MOSFET Selection
Most of the following MOSFET guidelines focus on the
challenge of obtaining high load-current capability
(> 5A) when using high-voltage (> 20V) AC adapters.
Low-current applications usually require less attention.
Choose a high-side MOSFET (N1/N3) that has conduc-
tion losses equal to the switching losses at the typical
battery voltage for maximum efficiency. Ensure that the
conduction losses at the minimum input voltage do not
exceed the package thermal limits or violate the overall
thermal budget. Ensure that conduction losses plus
switching losses at the maximum input voltage do not
exceed the package ratings or violate the overall ther-
mal budget.
Choose a synchronous rectifier (N2/N4) with the lowest
possible R DS(ON) . Ensure the gate is not pulled up by the
an insidious heat problem when maximum battery volt-
age is applied, due to the squared term in the CV 2 ? f
switching-loss equation. Reconsider the high-side
MOSFET chosen for adequate R DS(ON) at low battery
voltages if it becomes extraordinarily hot when subject-
ed to V+ (MAX) .
Calculating the power dissipation in N H (N1/N3) due to
switching losses is difficult since it must allow for quan-
tifying factors that influence the turn-on and turn-off
times. These factors include the internal gate resis-
tance, gate charge, threshold voltage, source induc-
tance, and PC board layout characteristics. The
following switching-loss calculation provides only a
very rough estimate and is no substitute for bench eval-
uation, preferably including verification using a thermo-
couple mounted on N H (N1/N3):
PD ( N H Switching ) =
+
2
V IN ( MAX ) I LOAD Q G ( SW ) f SW
I GATE
where C OSS is the output capacitance of N H (N1/N3),
Q G(SW) is the switch gate charge of N H , and I GATE is
the peak gate-drive source/sink current.
For the synchronous rectifier, the worst-case power dis-
sipation always occurs at maximum battery voltage:
PD ( N L ) = ? 1 ?
high-side switch turning on due to parasitic drain-to-gate
capacitance, causing crossconduction problems.
Switching losses are not an issue for the synchronous
rectifier in the buck topology since it is a zero-voltage
?
?
V OUT _ ? 2
? I LOAD R DS ( ON )
V IN ( MAX ) ?
(
)
? V ? 2
? I LOAD DS ( ON )
PD ( N H Re sis tan ce ) = ?
R
switched device when using the buck topology.
MOSFET Power Dissipation
Worst-case conduction losses occur at the duty-factor
extremes. For the high-side MOSFET, the worst-case
power dissipation (PD) due to the MOSFET’s R DS(ON)
occurs at the minimum battery voltage:
OUT _
? ?
? V IN ( MIN ) ?
The absolute worst case for MOSFET power dissipation
occurs under heavy overloads that are greater than
I LOAD(MAX) but are not quite high enough to exceed
the current limit and cause the fault latch to trip. To pro-
tect against this possibility, “overdesign” the circuit to
tolerate:
I LOAD = I LIMIT(HIGH) + (LIR / 2 ) x I LOAD(MAX)
where I LIMIT(HIGH) is the maximum valley current
allowed by the current-limit circuit, including threshold
tolerance and resistance variation.
______________________________________________________________________________________
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