参数资料
型号: MAX8798ETX+
厂商: Maxim Integrated Products
文件页数: 14/31页
文件大小: 0K
描述: IC INTERNAL-SW BOOST REG 36-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 50
应用: LCD 监视器,笔记本电脑显示器
电流 - 电源: 400µA
电源电压: 1.8 V ~ 6 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 36-WFQFN 裸露焊盘
供应商设备封装: 36-TQFN 裸露焊盘(6x6)
包装: 管件
Internal-Switch Boost Regulator with
Integrated 3-Channel Scan Driver for TFT LCDs
Pin Description (continued)
PIN
20
21
22
23
24
25
26
27
28, 29
30, 31
32
33
34
35
36
NAME
BGND
BOOST
OUT
POS
NEG
VCOM
SHDN
IN
LX
PGND
FB
COMP
AGND
GOFF
GON
EP
FUNCTION
Amplifier Ground
Operational Amplifier Supply Input. Connect to V MAIN (Figure 2) and bypass to BGND with a 1 μF or
greater ceramic capacitor.
Adjustable Sink-Current Output. OUT connects to the resistive voltage-divider at the op amp input POS
(between BOOST and GND) that determines the VCOM output voltage. I OUT lowers the divider voltage by
a programmable amount.
Operational Amplifier Noninverting Input
Operational Amplifier Inverting Input
Operational Amplifier Output
Shutdown Control Input. Pull SHDN low to disable the step-up regulator. The VCOM calibrator, op amp,
and scan driver functions remain enabled.
Step-Up Regulator Supply Input. Bypass IN to AGND (pin 34) with a 1μF or greater ceramic capacitor.
Switching Node. Connect inductor/catch diode here and minimize trace area for lowest EMI.
Power Ground. Source connection of the internal step-up regulator power switch.
Feedback Input. Reference voltage is 1.24V nominal. Connect external resistor-divider
midpoint here and minimize trace area. Set V OUT according to: V OUT = 1.24V (1 + R1/R2).
Compensation Input for Error Amplifier. Connect a series RC from COMP to AGND. Typical values are
180k and 470pF.
Ground
Gate-Off Supply. GOFF is the negative supply voltage for the CKV, CKVB, and STVP high-voltage driver
outputs. Bypass to PGND with a minimum of 0.1μF ceramic capacitor.
Gate-On Supply. GON is the positive supply voltage for the CKV, CKVB, and STVP high-voltage driver
outputs. Bypass to V MAIN or PGND with a minimum of 0.1μF ceramic capacitor.
Exposed Backside Pad. Connect to the analog ground plane through multiple vias to enhance thermal
performance.
14
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