参数资料
型号: MAX8798ETX+
厂商: Maxim Integrated Products
文件页数: 25/31页
文件大小: 0K
描述: IC INTERNAL-SW BOOST REG 36-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 50
应用: LCD 监视器,笔记本电脑显示器
电流 - 电源: 400µA
电源电压: 1.8 V ~ 6 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 36-WFQFN 裸露焊盘
供应商设备封装: 36-TQFN 裸露焊盘(6x6)
包装: 管件
Internal-Switch Boost Regulator with
Integrated 3-Channel Scan Driver for TFT LCDs
R PULLUP ≤
VCOM Calibrator Interface
The MAX8798 is a slave-only device with an I 2 C address
of 9Eh. The 2-wire I 2 C-bus-like serial interface (SCL and
SDA) is designed to attach to a 1.8V to 4V I 2 C bus.
Connect both SCL and SDA lines to the V DD supply
through individual pullup resistors. Calculate the
required value of the pullup resistors using:
t R
C BUS
where t R is the rise time in the Electrical Characteristics
table, and C BUS is the total capacitance on the bus.
The MAX8798 uses a nonstandard I 2 C interface proto-
col with mostly standard voltage and timing parame-
ters, as defined in the following subsections.
Bus Free
Both data and clock lines remain HIGH. Data transfers
can be initiated only when the bus is not busy (Figure 7).
START Condition (S)
Starting from an idle bus state (both SDA and SCL are
high), a HIGH to LOW transition of the SDA line while
the clock (SCL) is HIGH determines a START condition.
All commands must be preceded by a START condition
from a master device on the bus.
STOP Condition (P)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition from
the master device.
Data Valid
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal. The
data on the line must be changed during the LOW peri-
od of the clock signal. The master generates one clock
pulse per bit of data during write operations and the
slave device outputs 1 data bit per clock pulse during
read operations. Each data transfer is initiated with a
START condition and terminated with a STOP condition.
Two bytes are transferred between the START and
STOP conditions.
Slave Address
After generating a START condition, the bus master
transmits the slave address consisting of the 7-bit device
code (0b1001110 or 9Eh) for the MAX8798 (Figure 8).
For a read operation the 8th bit is 1 and for write opera-
tions it is 0. The MAX8798 monitors the bus for its corre-
sponding slave address continuously. It generates an
acknowledge bit if it recognizes its slave address and it
is not busy programming the EEPROM.
SDA
SCL
S
DATA LINE
CHANGE
P
BUS
FREE
START
CONDITION
STABLE
DATA VALID
OF DATA
ALLOWED
STOP
CONDITION
BUS
FREE
Figure 7. I 2 C Bus START, STOP, and Data Change Conditions
S
T
A
R
T
SLAVE ADDRESS
1001111
R/W
A
C
K
D6
D5
D4
DATA BYTE
D3 D2
D1
D0
P
R
O
G
A
C
K
S
T
O
P
READ BYTE: R/W = 1, MAX8798 OUTPUTS D6–D0 FOLLOWED BY PROG = 0
WRITE BYTE: R/W = 2, DATA = D6–D0, PROG = 1
PROGRAM EEPROM: R/W = 0, D6–D0 = DON'T CARE, PROG = 0
Figure 8. I 2 C Slave Address and Data Byte
______________________________________________________________________________________
25
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