参数资料
型号: MAX9856ETL+T
厂商: Maxim Integrated Products
文件页数: 16/46页
文件大小: 0K
描述: IC AUDIO CODEC 40TQFN-EP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: 音频编解码器
数据接口: 串行
分辨率(位): 18 b
ADC / DAC 数量: 2 / 2
三角积分调变:
S/N 比,标准 ADC / DAC (db): 77 / 91
动态范围,标准 ADC / DAC (db): 85 / 91
电压 - 电源,模拟: 1.71 V ~ 3.6 V
电压 - 电源,数字: 1.71 V ~ 3.6 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 40-WFQFN 裸露焊盘
供应商设备封装: 40-TQFN-EP(5x5)
包装: 带卷 (TR)
MAX9856
Low-Power Audio CODEC with
DirectDrive Headphone Amplifiers
______________________________________________________________________________________
23
REGISTER
FUNCTION
PCM
PCM Mode Select. PCM determines the format of the LRCLK_D and LRCLK_A signal:
0—The LRCLK_D and LRCLK_A signals have a 50% duty cycle. Left-channel audio is
transmitted during one state of and right-channel audio during the other state.
1—LRCLK_D and LRCLK_A are pulses that indicate the start of a frame of audio data
consisting of two channels. Following the frame sync pulse, 16 bits of left-channel data is
immediately followed by 16 bits of right-channel data. The DDLY and WS bits are ignored when
PCM = 1.
DHF
DAC High-Sample Rate Mode:
0—LRCLK_D is less than 50kHz. 8x FIR interpolation filter used.
1—LRCLK_D is greater than 50kHz. 4x FIR interpolation filter used.
WS
Word Size. This bit controls both the DAC and ADC:
0—16 bits.
1—18 bits.
The DAC interface can accept higher than 18-bit words but the additional least significant bits
are ignored.
DPLLEN
DAC PLL Enable:
0 (valid for slave and master mode)—The frequency of LRCLK_D is set by the DACNI divider
bits. In master mode, the MAX9856 generates LRCLK_D using the specified divide ratio. In
slave mode, the MAX9856 expects an LRCLK_D as specified by the divide ratio.
1 (valid for slave mode only)—A digital PLL locks on to any externally supplied LRCLK_D signal
regardless of the MCLK frequency. DHF must set high for sample rates above 50kHz.
DACNI
DAC LRCLK Divider. When DPLLEN is set low, the frequency of LRCLK_D is determined by
DACNI. See Table 6 for common DACNI values:
DACNI = (65536 x 96 x fLRCLK_D)/fPCLK for (DHF = 0).
DACNI = (65536 x 48 x fLRCLK_D)/fPCLK for (DHF = 1).
fLRCLK_D = LRCLK_D frequency.
fPCLK = Prescaled MCLK internal clock frequency (PCLK).
DAC Interface Register Bit Descriptions (continued)
LRCLK
MCLK (MHz)
PSCLK
8kHz
16kHz
32kHz
44.1kHz
48kHz
88.2kHz (DAC ONLY)
96kHz (DAC ONLY)
11.2896
001
116A
22D4
45A9
6000
687D
6000
687D
12
001
1062
20C5
4189
5A51
624E
5A51
624E
12.288
001
1000
2000
4000
5833
6000
5833
6000
13
001
F20
1E3F
3C7F
535F
5ABE
535F
5ABE
16.9344
010
B9C
1738
2E71
4000
45A9
4000
45A9
18.432
010
AAB
1555
2AAB
3ACD
4000
3ACD
4000
19.2
010
960
4B0
258
1B3
190
1B3
190
24
011
1062
20C5
4189
5A51
624E
5A51
624E
26
011
F20
1E3F
3C7F
535F
5ABE
535F
5ABE
27
011
E90
1D21
3A41
5048
5762
5048
5762
Table 6. Common DACNI and ADCNI Values
Note: Values in bold are exact integers that provide maximum full-scale performance.
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