参数资料
型号: MAX9856ETL+T
厂商: Maxim Integrated Products
文件页数: 32/46页
文件大小: 0K
描述: IC AUDIO CODEC 40TQFN-EP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: 音频编解码器
数据接口: 串行
分辨率(位): 18 b
ADC / DAC 数量: 2 / 2
三角积分调变:
S/N 比,标准 ADC / DAC (db): 77 / 91
动态范围,标准 ADC / DAC (db): 85 / 91
电压 - 电源,模拟: 1.71 V ~ 3.6 V
电压 - 电源,数字: 1.71 V ~ 3.6 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 40-WFQFN 裸露焊盘
供应商设备封装: 40-TQFN-EP(5x5)
包装: 带卷 (TR)
MAX9856
Low-Power Audio CODEC with
DirectDrive Headphone Amplifiers
38
______________________________________________________________________________________
TIME
EVENT
t0
Disable the headphone amplifiers. Set EN = 111 to enable the detection circuitry.
t0 + 24ms
IRQ set high. Indicates that the detection current has reached its final value and the impedance has been
stored in HSDETL, HSDETR, and JSDET.
tf -24ms
Once the impedance of HPL, HPR, and JACKSNS has been read, set EN = 000 to shut down the detection
circuitry.
tf
IRQ set high. Indicates that the detection circuitry is completely shut down and the headphone amplifiers can
be reenabled.
Table 15. Impedance Detection Routine
REG
B7
B6
B5
B4
B3
B2
B1
B0
0x1B
0
JDETEN
EN
Table 14. Headset Detect Control Register
BIT
FUNCTION
JDETEN
Jack Detection Enable
Sleep Mode—Enables pullups on HPL and JACKSNS to detect jack insertion. LSNS and JKSNS are not
valid unless JDETEN = 1 and
SHDN = 0.
Normal Mode—Enables the comparator circuitry on JACKSNS to detect voltage changes. JKMIC is not valid
unless JDETEN = 1 and the microphone circuitry is enabled.
Impedance Detection Enable. Enables the impedance detection circuitry for HPL, HPR, and JACKSNS.
When EN = 000 HSDETL, HSDETR, and JSDET are set to 11. See Table 2, Status Register Bit Description
for details on reading the load impedance.
IMPEDANCE DETECTION ENABLE DESCRIPTION
EN
DESCRIPTION
000
Disabled
1xx
JACKSNS pin impedance sense enabled
x1x
HPR pin impedance sense enabled
EN
xx1
HPL pin impedance sense enabled
Headset Detection Register Bit Description
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