参数资料
型号: MAX9856ETL+T
厂商: Maxim Integrated Products
文件页数: 38/46页
文件大小: 0K
描述: IC AUDIO CODEC 40TQFN-EP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: 音频编解码器
数据接口: 串行
分辨率(位): 18 b
ADC / DAC 数量: 2 / 2
三角积分调变:
S/N 比,标准 ADC / DAC (db): 77 / 91
动态范围,标准 ADC / DAC (db): 85 / 91
电压 - 电源,模拟: 1.71 V ~ 3.6 V
电压 - 电源,数字: 1.71 V ~ 3.6 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 40-WFQFN 裸露焊盘
供应商设备封装: 40-TQFN-EP(5x5)
包装: 带卷 (TR)
PCB Layout and Bypassing
Proper layout and grounding are essential for optimum
performance. Use large traces for the power-supply
inputs and amplifier outputs to minimize losses due to
parasitic trace resistance. Proper grounding improves
audio performance, minimizes crosstalk between chan-
nels, and prevents any switching noise from coupling
into the audio signal. Connect AGND, DGND, CPGND,
and PGND together at a single point on the PCB using
the star grounding technique. Route DGND, CPGND,
and all traces that carry switching transients or digital
signals separately from AGND and the analog audio
signal paths. Ground all components associated with
the charge pump to CPGND (CPVSS bypassing and
CPVDD bypassing). Connect all digital I/O termination
to DGND including DVDD and DVDDS2 bypassing.
Bypass REF and MICBIAS to AGND.
Connect PVSS and SVSS together at the device and
place the charge-pump hold capacitor (C2) as close to
SVSS as possible and ground to CPGND. Bypass
CPVDD with a 1F capacitor to CPGND and place the
bypass capacitor as close to the device as possible.
The MAX9856 thin QFN package features an exposed
thermal pad on its underside. This pad lowers the pack-
age’s thermal resistance by providing a direct heat
conduction path from the die to the PCB. Connect the
exposed thermal pad to AGND.
An evaluation kit (EV Kit) is available to provide an
example layout for the MAX9856. The EV Kit allows
quick setup of the MAX9856 and includes easy-to-use
software allowing all internal registers to be controlled.
MAX9856
Low-Power Audio CODEC with
DirectDrive Headphone Amplifiers
______________________________________________________________________________________
43
Chip Information
PROCESS: BiCMOS
Pin Configuration
MAX9856
THIN QFN
(6mm x 6mm)
TOP VIEW
35
36
34
33
12
11
13
LINEIN2
PREG
NREG
MBIAS
REF
14
LINEIN1
SDIN
BCLK
LRCLK_D
DVDDS2
LRCLK_A
MCLK
IRQ
SDA
12
INLP
45
6
7
27
28
29
30
26
24 23
22
MICL
MICGND
CPGND
C1N
PVSS
SVSS
AUXIN
SDOUT
3
25
37
MICR
HPR
38
39
*EP
+
* EP = EXPOSED PAD.
40
MICBIAS
AGND
JACKSNS
HPL
AVDD
HGNDSNS
INLN
32
15
C1P
DGND
31
16
17
18
19
20 CPVDD
LGNDSNS
LOUTL
LOUTR
SCL
89
10
21
DVDD
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