参数资料
型号: MB90F523PFV-G
厂商: FUJITSU LTD
元件分类: 微控制器/微处理器
英文描述: 16-BIT, FLASH, 16 MHz, MICROCONTROLLER, PQFP120
封装: PLASTIC, QFP-120
文件页数: 54/127页
文件大小: 2636K
代理商: MB90F523PFV-G
MB90520 Series
32
s PERIPHERALS
1. I/O Port
(1) Input/Output Port
Port 0 through 8, A are general-purpose I/O ports having a combined function as a resource input. The input
output ports function as general-purpose I/O port only in the single-chip mode.
Operation as output port
The pin is configured as an output port by setting the corresponding bit of the DDR register to “1”.
Writing data to PDR register when the port is configured as output, the data is retained in the output latch in
the PDR and directly output to the pin.
The value of the pin (the same value retained in the output latch of PDR) can be read out by reading the PDR
register.
Note: When a read-modify-write type instruction (e.g. bit set instruction) is performed to the port data register,
the destination bit of the operation is set to the specified value, not affecting the bits configured by the
DDR register for output, however, values of bits configured by the DDR register as inputs are changed
because input values to the pins are written into the output latch. To avoid this situation, configure the
pins by the DDR register as output after writing output data to the PDR register when configuring the bit
used as input as outputs.
Operation as input port
The pin is configured as an input by setting the corresponding bit of the DDR register to “0”.
When the pin is configured as an input, the output buffer is turned-off and the pin is put into a high-impedance
status.
When a data is written into the PDR register, the data is retained in the output latch of the PDR, but pin outputs
are unaffected.
Reading the PDR register reads out the pin level (“0” or “1”).
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