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参数资料
| 型号： | MB90F523PFV-G |
| 厂商： | FUJITSU LTD |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, FLASH, 16 MHz, MICROCONTROLLER, PQFP120 |
| 封装： | PLASTIC, QFP-120 |
| 文件页数： | 8/127页 |
| 文件大小： | 2636K |
| 代理商： | MB90F523PFV-G |
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105
MB90520 Series
s INSTRUCTIONS (340 INSTRUCTIONS)
Table 1
Description of items in instruction list
Number of execution cycles
The number of cycles required for instruction execution is acquired by adding the number of cycles for each
instruction, a corrective value depending on the condition, and the number of cycles required for program fetch.
Whenever the instruction being executed exceeds the two-byte (word) boundary, a program on an internal
ROM connected to a 16-bit bus is fetched. If data access is interfered with, therefore, the number of execution
cycles is increased.
For each byte of the instruction being executed, a program on a memory connected to an 8-bit external data
bus is fetched. If data access in interfered with, therefore, the number of execution cycles is increased.
When a general-purpose register, an internal ROM, an internal RAM, an internal I/O device, or an external
bus is accessed during intermittent CPU operation, the CPU clock is suspended by the number of cycles
specified by the CG1/0 bit of the low-power consumption mode control register. When determining the number
Item
Description
Mnemonic
English upper case and symbol: Described directly in assembler code.
English lower case: Converted in assembler code.
Number of letters after English lower case: Describes bit width in code.
#
Describes number of bytes.
~
Describes number of cycles.
m : For branch operation
n : For non-branch operation
For other letters in other items, refer to table 4.
RG
Describes the number of times the register is accessed during instruction execution. Used to
calculate a corrective value for CPU intermittent operation.
B
Describes correction value for calculating number of actual cycles (refer to table 5).
Number of actual cycles is calculated by adding values in the ~section and section B.
Operation
Describes operation of instructions.
LH
Describes a special operation to the upper 8-bit of the lower 16-bit of the accumulator.
Z : Transfer 0.
X : Sign-extend and transfer.
– : No transmission
AH
Describes a special operation to the upper 16-bit of the accumulator.
* : Transmit from AL to AH.
– : No transfer.
Z : Transfer 00H to AH.
X : Sign-extend AL and transfer 00H or FFH to AH.
I
Describe status of I (interrupt enable), S (stack), T (sticky bit), N (negative), Z (zero),
V (overflow), and C (carry) flags.
* : Changes after execution of instruction.
– : No changes.
S : Set after execution of instruction.
R : Reset after execution of instruction.
S
T
N
Z
V
C
RMW
Describes whether or not the instruction is a read-modify-write type (a data is read out from
memory etc. in single cycle, and the result is written into memory etc.).
* : Read-modify-write instruction
– : Not read-modify-write instruction
Note: Not used to addresses having different functions for reading and writing operations.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MB90F543GPF-GE1 | 功能描述:IC MCU 16BIT 制造商:cypress semiconductor corp 系列:F2MC-16LX MB90540G 包装:托盘 零件状态:在售 核心处理器:F2MC-16LX 核心尺寸:16-位 速度:16MHz 连接性:CAN，EBI/EMI，SCI，串行输入/输出，UART/USART 外设:POR，WDT I/O 数:81 程序存储容量:128KB（128K x 8） 程序存储器类型:闪存 EEPROM 容量:- RAM 容量:6K x 8 电压 - 电源（Vcc/Vdd）:4.5 V ~ 5.5 V 数据转换器:A/D 8x8/10b 振荡器类型:外部 工作温度:-40°C ~ 105°C（TA） 封装/外壳:100-BQFP 供应商器件封装:100-PQFP（20x14） 标准包装:66 |
| MB90F543GPFR-GE1 | 制造商:FUJITSU 功能描述: |
| MB90F543GSPFR-GE1 | 制造商:FUJITSU 功能描述: |
| MB90F543GSPMCR-GE1 | 制造商:FUJITSU 功能描述: |
| MB90F543PFR-GE1 | 制造商:FUJITSU 功能描述: |
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