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| 型号： | MB9AF314MPMC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, FLASH, 40 MHz, RISC MICROCONTROLLER, PQFP80 |
| 封装： | 0.50 MM PITCH, PLASTIC, LQFP-80 |
| 文件页数： | 9/114页 |
| 文件大小： | 1357K |
| 代理商： | MB9AF314MPMC |
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ATmega48PA/88PA/168PA [DATASHEET]
9223F–AVR–04/14
106
Figure 16-4 shows a block diagram of the output compare unit. The small “n” in the register and bit names indicates the
device number (n = 1 for Timer/Counter 1), and the “x” indicates output compare unit (A/B). The elements of the block
diagram that are not directly a part of the output compare unit are gray shaded.
Figure 16-4. Output Compare Unit, Block Diagram
The OCR1x register is double buffered when using any of the twelve pulse width modulation (PWM) modes. For the normal
and clear timer on compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes
the update of the OCR1x compare register to either TOP or BOTTOM of the counting sequence. The synchronization
prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.
The OCR1x register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has
access to the OCR1x buffer register, and if double buffering is disabled the CPU will access the OCR1x directly. The content
of the OCR1x (buffer or compare) register is only changed by a write operation (the Timer/Counter does not update this
register automatically as the TCNT1 and ICR1 register). Therefore OCR1x is not read via the high byte temporary register
(TEMP). However, it is a good practice to read the low byte first as when accessing other 16-bit registers. Writing the OCR1x
registers must be done via the TEMP register since the compare of all 16 bits is done continuously. The high byte (OCR1xH)
has to be written first. When the high byte I/O location is written by the CPU, the TEMP register will be updated by the value
written. Then when the low byte (OCR1xL) is written to the lower eight bits, the high byte will be copied into the upper 8-bits
of either the OCR1x buffer or OCR1x compare register in the same system clock cycle.
For more information of how to access the 16-bit registers refer to Section 16.3 “Accessing 16-bit Registers” on page 100.
16.7.1 Force Output Compare
In non-PWM waveform generation modes, the match output of the comparator can be forced by writing a one to the force
output compare (FOC1x) bit. Forcing compare match will not set the OCF1x Flag or reload/clear the timer, but the OC1x pin
will be updated as if a real compare match had occurred (the COM11:0 bits settings define whether the OC1x pin is set,
cleared or toggled).
OCRnxL Buf. (8-bit)
OCRnxH Buf. (8-bit)
OCRnx Buffer (16-bit Register)
TEMP (8-bit)
OCRnxL (8-bit)
OCFnx (Int. Req.)
OCRnxH (8-bit)
OCRnx (16-bit Register)
= (16-bitComparator)
WGMn3:0
COMnx1:0
Waveform Generator
TCNTnL (8-bit)
TCNTnH (8-bit)
TCNTn (16-bit Counter)
DATA BUS (8-bit)
OCnx
TOP
BOTTOM
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