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参数资料
| 型号： | MBM29F800TA-70PFTN-E1 |
| 厂商： | SPANSION LLC |
| 元件分类： | PROM |
| 英文描述： | 512K X 16 FLASH 5V PROM, 70 ns, PDSO48 |
| 封装： | PLASTIC, TSOP1-48 |
| 文件页数： | 9/49页 |
| 文件大小： | 693K |
| 代理商： | MBM29F800TA-70PFTN-E1 |
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MBM29F800TA-55/-70/-90/MBM29F800BA-55/-70/-90
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be supplied by the system at this particular instance of time. Hence, Data Polling must be performed at the
memory location which is being programmed.
Any commands written to the chip during this period will be ignored. If hardware reset occurs during the
programming operation, it is impossible to guarantee the data are being written.
Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be
programmed back to a “1”. Attempting to do so may either hang up the device or result in an apparent success
according to the data polling algorithm but a read from Read/Reset mode will show that the data is still “0”. Only
erase operations can convert “0”s to “1”s.
“Embedded ProgramTM Algorithm” in s FLOW CHART illustrates the Embedded Programming AlgorithmTM using
typical command strings and bus operations.
Chip Erase
Chip erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the chip erase command.
Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded EraseTM
Algorithm command sequence the device will automatically program and verify the entire memory for an all zero
data pattern prior to electrical erase. The system is not required to provide any controls or timings during these
operations.
The automatic erase begins on the rising edge of the last WE pulse in the command sequence and terminates
when the data on DQ7 is “1” (see Write Operation Status section) at which time the device returns to read the
mode.
“Embedded EraseTM Algorithm” in s FLOW CHART illustrates the Embedded Erase Algorithm using typical
command strings and bus operations.
Sector Erase
Sector erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the Sector Erase command. The sector
address (any address location within the desired sector) is latched on the falling edge of WE, while the command
(Data = 30h) is latched on the rising edge of WE. After time-out of 50 s from the rising edge of the last sector
erase command, the sector erase operation will begin.
Multiple sectors may be erased concurrently by writing the six bus cycle operations on “MBM29F800TA/BA
Command Definitions” in s DEVICE BUS OPERATION. This sequence is followed with writes of the Sector
Erase command to addresses in other sectors desired to be concurrently erased. The time between writes must
be less than 50 s otherwise that command will not be accepted and erasure will start. It is recommended that
processor interrupts be disabled during this time to guarantee this condition. The interrupts can be re-enabled
after the last Sector Erase command is written. A time-out of 50 s from the rising edge of the last WE will initiate
the execution of the Sector Erase command(s). If another falling edge of the WE occurs within the 50 s time-
out window the timer is reset. (Monitor DQ3 to determine if the sector erase timer window is still open, see section
DQ3, Sector Erase Timer.) Any command other than Sector Erase or Erase Suspend during this time-out period
will reset the devices to the read mode, ignoring the previous command string. Resetting the device once
execution has begun will corrupt the data in that sector. In that case, restart the erase on those sectors and
allow them to complete. (Refer to the Write Operation Status section for Sector Erase Timer operation.) Loading
the sector erase buffer may be done in any sequence and with any number of sectors (18 to 0).
Sector erase does not require the user to program the devices prior to erase. The device automatically programs
all memory locations in the sector(s) to be erased prior to electrical erase. When erasing a sector or sectors the
remaining unselected sectors are not affected. The system is not required to provide any controls or timings
during these operations.
The automatic sector erase begins after the 50 s time out from the rising edge of the WE pulse for the last
sector erase command pulse and terminates when the data on DQ7 is “1” (see Write Operation Status section)
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MBM29F800TA-70PFTN-SFL(E1) | 制造商:Fujitsu 功能描述: |
| MBM29F800TA-70PFTN-SFLE1 | 制造商:Spansion 功能描述:IC 5V 8M FLASH |
| MBM29F800TA-70PFTR | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:8M (1M X 8/512K X 16) BIT |
| MBM29F800TA-90 | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:8M (1M X 8/512K X 16) BIT |
| MBM29F800TA-90PF | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:8M (1M X 8/512K X 16) BIT |
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