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参数资料
| 型号： | MC16S2CPU20B1 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, 20.97 MHz, MICROCONTROLLER, PQFP100 |
| 封装： | TQFP-100 |
| 文件页数： | 35/104页 |
| 文件大小： | 812K |
| 代理商： | MC16S2CPU20B1 |
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MOTOROLA
MC68HC16S2
36
MC68HC16S2TS/D
IPL[2:0] — Interrupt Priority Level
If the space field is set for CPU space, chip-select logic can be used for interrupt acknowledge. During
an interrupt acknowledge cycle, the priority level on address lines ADDR[3:1] is compared to the value
in the IPL field. If the values are the same, a chip-select is asserted, provided that other option register
conditions are met. Table 28 shows IPL field encoding.
This field only affects the response of chip-selects and does not affect interrupt recognition by the CPU.
Any level means that chip-select is asserted regardless of the level of the interrupt acknowledge cycle.
AVEC — Autovector Enable
0 = External interrupt vector enabled
1 = Autovector enabled
This field selects one of two methods of acquiring an interrupt vector number during an external interrupt
acknowledge cycle.
If the chip-select is configured to trigger on an interrupt acknowledge cycle (SPACE[1:0] = %00) and
the AVEC field is set to one, the chip-select circuit generates an internal AVEC signal in response to an
external interrupt cycle, and the SIM supplies an automatic vector number. Otherwise, the vector num-
ber must be supplied by the requesting device. An internal autovector is generated only in response to
interrupt requests from the SIM IRQ pins. Interrupt requests from other IMB modules are ignored.
The AVEC bit must not be used in synchronous mode, as autovector response timing can vary because
of ECLK synchronization.
3.6.5 Port C Data Register
Bit values in port C determine the state of chip-select pins used for discrete output. When a pin is as-
signed as a discrete output, the value in this register appears at the output. This is a read/write register.
Bit 7 is not used. Writing to this bit has no effect, and it always returns zero when read.
Table 27 Address Space Bit Encodings
SPACE[1:0]
Address Space
00
CPU space
01
User space
10
Supervisor space
11
Supervisor/User space
Table 28 Interrupt Priority Level Field Encoding
IPL[2:0]
Interrupt Priority Level
000
Any level
001
1
010
2
011
3
100
4
101
5
110
6
111
7
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