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参数资料
| 型号： | MC16S2CPU20B1 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, 20.97 MHz, MICROCONTROLLER, PQFP100 |
| 封装： | TQFP-100 |
| 文件页数： | 44/104页 |
| 文件大小： | 812K |
| 代理商： | MC16S2CPU20B1 |
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MOTOROLA
MC68HC16S2
44
MC68HC16S2TS/D
1.
FC[2:0] are driven to %111 (CPU space) encoding.
2.
The address bus is driven as follows: ADDR[23:20] = %1111; ADDR[19:16] = %1111,
which indicates that the cycle is an interrupt acknowledge CPU space cycle; ADDR[15:4]
= %111111111111; ADDR[3:1] = the priority of the interrupt request being acknowledged;
and ADDR0 = %1.
3.
The request level is latched from the address bus into the IP mask field in the condition
code register.
D. Modules or external peripherals that have requested interrupt service decode the priority value
on ADDR[3:1]. If request priority is the same as acknowledged priority, arbitration by IARB
contention takes place.
E. After arbitration, the interrupt acknowledge cycle is completed in one of the following ways:
1.
When there is no contention (IARB = %0000), the spurious interrupt monitor asserts BERR,
and the CPU16 generates the spurious interrupt vector number.
2.
The dominant interrupt source supplies a vector number and DSACK signals appropriate
to the access. The CPU16 acquires the vector number.
3.
The internal AVEC signal is asserted by the dominant interrupt source and the CPU16 gen-
erates an autovector number corresponding to interrupt priority.
4.
The bus monitor asserts BERR and the CPU16 generates the spurious interrupt vector
number.
F. The vector number is converted to a vector address.
G. The content of the vector address is loaded into the PC, and the processor transfers control to
the exception handler routine.
3.10 Factory Test Block
The test submodule supports scan-based testing of the various MCU modules. It is integrated into the
SIM to support production testing.
Test submodule registers are intended for Motorola use. Register names and addresses are provided
to indicate that these addresses are occupied.
SIMTR — System Integration Module Test Register
$YFFA02
SIMTRE — System Integration Module Test Register (E Clock)
$YFFA08
TSTMSRA — Master Shift Register A
$YFFA30
TSTMSRB — Master Shift Register B
$YFFA32
TSTSC — Test Module Shift Count
$YFFA34
TSTRC — Test Module Repetition Count
$YFFA36
CREG — Test Module Control Register
$YFFA38
DREG — Test Module Distributed Register
$YFFA3A
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For More Information On This Product,
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