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| 型号： | MC16S2CPU20B1 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, 20.97 MHz, MICROCONTROLLER, PQFP100 |
| 封装： | TQFP-100 |
| 文件页数： | 42/104页 |
| 文件大小： | 812K |
| 代理商： | MC16S2CPU20B1 |
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MOTOROLA
MC68HC16S2
42
MC68HC16S2TS/D
3.9 Interrupts
Interrupt recognition and servicing involve complex interaction between the CPU16, the SIM, and a de-
vice or module requesting interrupt service.
The CPU16 provides seven levels of interrupt priority (1–7), seven automatic interrupt vectors, and 200
assignable interrupt vectors. All interrupts with priorities less than seven can be masked by the interrupt
priority (IP) field in the condition code register. The CPU16 handles interrupts as a type of asynchronous
expression.
There are seven interrupt request signals (IRQ[7:1]). These signals are used internally on the IMB, and
there are corresponding pins for external interrupt service requests. The CPU treats all interrupt re-
quests as though they come from internal modules — external interrupt requests are treated as interrupt
service requests from the SIM. Each of the interrupt request signals corresponds to an interrupt priority
level. IRQ1 has the lowest priority and IRQ7 the highest.
Interrupt recognition is determined by interrupt priority level and interrupt priority mask value. The inter-
rupt priority mask consists of three bits (IP[2:0]) in the CPU16 condition code register. Binary values
%000 to %111 provide eight priority masks. Masks prevent an interrupt request of a priority less than
or equal to the mask value from being recognized and processed. IRQ7, however, is always recognized,
even if the mask value is %111.
IRQ[7:1] are active-low level-sensitive inputs. The low on the pin must remain asserted until an interrupt
acknowledge cycle corresponding to that level is detected.
IRQ7 is transition-sensitive as well as level-sensitive: a level 7 interrupt is not detected unless a falling
edge transition is detected on the IRQ7 line. This prevents redundant servicing and stack overflow. A
non-maskable interrupt is generated each time IRQ7 is asserted as well as each time the priority mask
changes from %111 to a lower number while IRQ7 is asserted.
Interrupt requests are sampled on consecutive falling edges of the system clock. Interrupt request input
circuitry has hysteresis: to be valid, a request signal must be asserted for at least two consecutive clock
periods. Valid requests do not cause immediate exception processing, but are left pending. Pending re-
quests are processed at instruction boundaries or when exception processing of higher-priority excep-
tions is complete.
The CPU16 does not latch the priority of a pending interrupt request. If an interrupt source of higher
priority makes a service request while a lower priority request is pending, the higher priority request is
serviced. If an interrupt request with a priority equal to or lower than the current IP mask value is made,
the CPU16 does not recognize the occurrence of the request. If simultaneous interrupt requests of dif-
ferent priorities are made, and both have a priority greater than the mask value, the CPU16 recognizes
the higher-level request.
3.9.1 Interrupt Acknowledge and Arbitration
When the CPU16 detects one or more interrupt requests of a priority higher than the interrupt priority
mask value, it places the interrupt request level on the address bus and initiates a CPU space read cy-
cle. The request level serves two purposes: it is decoded by modules or external devices that have re-
quested interrupt service, to determine whether the current interrupt acknowledge cycle pertains to
them, and it is latched into the IP mask field in the CPU16 condition code register, to preclude further
interrupts of lower priority during interrupt service.
Modules or external devices that have requested interrupt service must decode the interrupt priority
mask value placed on the address bus during the interrupt acknowledge cycle and respond if the priority
of the service request corresponds to the mask value. However, before modules or external devices
respond, interrupt arbitration takes place.
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