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参数资料
型号： MC56F8033VLC
厂商： FREESCALE SEMICONDUCTOR INC
元件分类： 微控制器/微处理器
英文描述： 16-BIT, FLASH, 32 MHz, MICROCONTROLLER, PQFP32
封装： ROHS COMPLIANT, PLASTIC, LQFP-32
文件页数： 109/157页
文件大小： 2117K
代理商： MC56F8033VLC
Functional Description
56F8033/56F8023 Data Sheet, Rev. 6
Freescale Semiconductor
55
For further information, see Table 4-2, Interrupt Vector Table Contents.
5.3 Functional Description
The Interrupt Controller is a slave on the IPBus. It contains registers that allow each of the 64 interrupt
sources to be set to one of four priority levels (excluding certain interrupts that are of fixed priority). Next,
all of the interrupt requests of a given level are priority encoded to determine the lowest numerical value
of the active interrupt requests for that level. Within a given priority level, number 0 is the highest priority
and number 63 is the lowest.
5.3.1
Normal Interrupt Handling
Once the INTC has determined that an interrupt is to be serviced and which interrupt has the highest
priority, an interrupt vector address is generated. Normal interrupt handling concatenates the Vector Base
Address (VBA) and the vector number to determine the vector address, generating an offset into the vector
table for each interrupt.
5.3.2
Interrupt Nesting
Interrupt exceptions may be nested to allow an IRQ of higher priority than the current exception to be
serviced. The 56800E core controls the masking of interrupt priority levels it will accept by setting the I0
and I1 bits in its status register.
The IPIC bits of the ICTRL register reflect the state of the priority level being presented to the 56800E
core.
Table 5-1 Interrupt Mask Bit Definition
SR[9] (I1)
SR[8] (I0)
Exceptions Permitted
Exceptions Masked
0
Priorities 0, 1, 2, 3
None
0
1
Priorities 1, 2, 3
Priority 0
1
0
Priorities 2, 3
Priorities 0, 1
1
Priority 3
Priorities 0, 1, 2
Table 5-2 Interrupt Priority Encoding
IPIC_VALUE[1:0]
Current Interrupt
Priority Level
Required Nested
Exception Priority
00
No interrupt or SWILP
Priorities 0, 1, 2, 3
01
Priority 0
Priorities 1, 2, 3
10
Priority 1
Priorities 2, 3
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