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参数资料
型号： MC56F8033VLC
厂商： FREESCALE SEMICONDUCTOR INC
元件分类： 微控制器/微处理器
英文描述： 16-BIT, FLASH, 32 MHz, MICROCONTROLLER, PQFP32
封装： ROHS COMPLIANT, PLASTIC, LQFP-32
文件页数： 128/157页
文件大小： 2117K
代理商： MC56F8033VLC
56F8033/56F8023 Data Sheet, Rev. 6
72
Freescale Semiconductor
5.6.11.2
Fast Interrupt 0 Vector Address High (FIVAH0)—Bits 4–0
The upper five bits of the vector address used for Fast Interrupt 0. This register is combined with FIVAL0
to form the 21-bit vector address for Fast Interrupt 0 defined in the FIM0 register.
5.6.12
Fast Interrupt 1 Match Register (FIM1)
Figure 5-14 Fast Interrupt 1 Match Register (FIM1)
5.6.12.1
Reserved—Bits 15–6
This bit field is reserved. Each bit must be set to 0.
5.6.12.2
Fast Interrupt 1 Vector Number (FAST INTERRUPT 1)—Bits 5–0
These values determine which IRQ will be Fast Interrupt 1. Fast Interrupts vector directly to a service
routine based on values in the Fast Interrupt Vector Address registers without having to go to a jump table
first. IRQs used as Fast Interrupts must be set to priority level 2. Unexpected results will occur if a Fast
Interrupt vector is set to any other priority. A Fast Interrupt automatically becomes the highest priority
level 2 interrupt, regardless of its location in the interrupt table prior to being declared as Fast Interrupt.
Fast Interrupt 0 has priority over Fast Interrupt 1. To determine the vector number of each IRQ, refer to
the vector table.
5.6.13
Fast Interrupt 1 Vector Address Low Register (FIVAL1)
Figure 5-15 Fast Interrupt 1 Vector Address Low Register (FIVAL1)
5.6.13.1
Fast Interrupt 1 Vector Address Low (FIVAL1)—Bits 15–0
The lower 16 bits of the vector address used for Fast Interrupt 1. This register is combined with FIVAH1
to form the 21-bit vector address for Fast Interrupt 1 defined in the FIM1 register.
5.6.14
Fast Interrupt 1 Vector Address High (FIVAH1)
Figure 5-16 Fast Interrupt 1 Vector Address High Register (FIVAH1)
Base + $B
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
0
FAST INTERRUPT 1
Write
RESET
00000
0000000
0000
Base + $C
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
FAST INTERRUPT 1 VECTOR ADDRESS LOW
Write
RESET
00000
0000000
0000
Base + $D
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
0
FAST INTERRUPT 1 VECTOR
ADDRESS HIGH
Write
RESET
00000
0000000
0000
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